Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Glitch free clock select

Abstract: Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

Double-edge-triggered flip-flop providing two data transitions per clock cycle

Abstract: An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement

Abstract: Clock gating is one of the most effective techniques to reduce clock tree power. Although it has already been studied considerably, most of the previous works are restricted to either register transfer level (RTL) or clock tree synthesis stage. Clock gating design at RTL is coarse and it pays no attention to the physical information, therefore, it often results in large wirelength overhead. While if clock gating is considered only at clock tree synthesis, the optimization space is largely limited due to the fixing of registers. To fully use the logical and physical information between registers, we propose a new flow for low-power gated clock tree design in this work. It mainly includes three parts: gated clock tree aware register placement, gated clock tree construction, and incremental placement. Compared with the previous works on clock gating, our algorithm reduces the clock tree power with much fewer gating logics, therefore, the overhead to the placement is also reduced.

Clock distribution network with process, supply-voltage, and temperature compensation

Abstract: Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

Abstract: In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical electromagnetic-interference reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional aperiodic modulating signal is used, the clock can be recovered by exploiting a standard clock and data recovery circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13-μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 psrms, while the chip active area is 0.27 0.78 × mm2 and the power consumption is as low as 14.7 mW.