Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Clock generating circuit having high resolution of delay time between external clock signal and internal clock signal

Abstract: A clock generating circuit synchronizes an internal clock signal with an external clock signal, and has a delay circuit implemented by a series of delay stages connected through pairs of signal transfer lines to one another; each of the delay stages has a series combination of a first charging circuit and a first discharging circuit connected between a positive power line and a ground line and a series combination of a second charging circuit and a second discharging circuit connected in parallel to the first series combination, and each pair of signal transfer lines is connected between the first series combination of one of the delay stage and the second series combination of the next delay series; a potential edge signal is propagated through charging/discharging operations toward a certain delay stage during a first time period equal to the pulse period of the external clock signal, and returns to the first delay stage so as to generate a one-shot pulse in the next pulse period; even if the pulse period fluctuates, the delay circuit changes the turning point of the potential edge signal, and makes the internal clock signal strictly synchronous with the external clock signal.

Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency

Abstract: A method and apparatus for reducing the power consumption of an integrated circuit when the core logic of the integrated circuit is in the quiescent or idle state. The method and apparatus includes a phase locked loop (PLL) circuit for generating an internal clock, wherein the frequency of the internal clock is at a predetermined multiple of the frequency of the global clock signal. When the integrated circuit is quiescent, the present invention provides circuitry which permits the internal clock to be slowed to a lower frequency or the internal clock to be frozen to reduce power consumption.

Method and apparatus for setting and compensating read latency in a high speed DRAM

Abstract: An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock (129) is produced from the external clock signal (116) in a delay lock loop circuit (120) and a start signal (118), produced in response to a read command (112), is passed through a delay circuit (132) slaved with the delay lock loop (120) so that the read clock signal (129) and a delayed start signal (174) are subject to the same internal timing variations. The delayed start signal (174) is used to thereby control the output of read data by the read clock signal (129).

Synchronizing logic avoiding metastability

Abstract: According to the invention an apparatus is provided comprising a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit comprising an input circuit coupled to the first circuit and receiving signals therefrom. The apparatus further comprises a control circuit for controlling possible metastability situations in a communication between the first circuit and the second circuit. The control circuit receives as input the first clock signal and the second clock signal and comprises means for providing a shifting of at least one of the both clock signals, or parts thereof, in such a way that a possible metastable state of the input circuit is avoidable. A possible metastability situation in an apparatus according to the invention is controlled by monitoring the first clock signal and the second clock signal. When a possible metastability situation has been detected, at least one of the both clock signals, or parts thereof, is shifted, preferably advanced or delayed, in such a way that a possible metastable state of the input circuit can be avoided.

Changing of operating voltage in semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes a module configured to operate based on a clock signal, a voltage controlling unit configured to change a power supply voltage supplied to the module, a clock generating unit configured to supply the clock signal to the module, and a test circuit configured to operate at the power supply voltage based on the clock signal to emulate a delay of a critical path provided in the module, thereby testing whether the module properly operates at the power supply voltage, wherein the clock generating unit supplies a different signal, in place of the clock signal, to the module while the voltage controlling unit is changing the power supply voltage.