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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
George W. Conner1
01 May 1995
TL;DR: In this paper, a system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period was proposed, where each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals.
Abstract: A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals and local programmable delay means for providing a timing signal after a delay interval following each local output, the resolution of the local delay means being greater than that of the clock

39 citations

Patent
16 Apr 1992
TL;DR: In this article, a serial access memory capable of reading out data serially at a speed double the writing speed was proposed, implemented as a semiconductor chip having an edge detecting circuit and a clock doubling circuit for data read-out mounted thereon.
Abstract: A serial access memory capable of reading out data serially at a speed double the writing speed. The memory is implemented as a semiconductor chip having an edge detecting circuit and a clock doubling circuit for data read-out mounted thereon. The edge detecting circuit detects the positive-going and negative-going edges of a clock fed to the chip from the outside. In response to the output of the edge detecting circuit, the clock doubling circuit generates a read clock having a frequency double the frequency of the external clock. The double-speed clock generated within the chip reduces the cost of the memory.

39 citations

Proceedings ArticleDOI
24 Nov 2008
TL;DR: CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.
Abstract: At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

39 citations

Patent
10 Feb 2004
TL;DR: In this paper, a digital duty cycle correction circuit and method for a multi-phase clock is presented, in which duty cycle information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle corrections method.
Abstract: Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.

39 citations

Patent
14 Apr 1997
TL;DR: In this paper, a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy, is realized.
Abstract: It is to realize a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy. An input terminal D of a through latch circuit LTC11 is connected to an input line of an enable signal EN, an inversion clock input terminal G is connected to the input line of the clock signal, one input terminal of a NAND gate NAND11 is connected to an output terminal Q of a through latch circuit LTC11, the other input terminal is connected to the input terminal of the clock signal CK, and the output terminal is connected to the input terminal of an inverter INV11. Then, in the through latch circuit LTC11, the enable signal EN is sampled at the rising edge of the clock signal CK, and according to the value, the clock pulse immediately after the sampling is passed or blocked by the logical gate LGT comprising a NAND gate NAND11 and an inverter INV11.

39 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884