Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

An efficent clustering algorithm for low power clock tree synthesis

Abstract: Clocks are known to be major source of power consumption in digital circuits, especially in high performance microprocessors. With the technology scaling, the increasingly capacitive interconnects contribute to more than 40% of the local clock power. In this paper, we propose a clustering algorithm for them inimization of the power in local clock tree, which is shown to be equivalent to the minimization of interconnect capacitance in the tree. Given a set of sequentials and their locations, clustering is performed to determine the clockbuffers that are required to synchronize the sequentials, where a cluster implies that a clock buffer drives all the sequentials in the cluster. The clustering algorithm uses minimum spanning tree (MST) metric to estimate the interconnect capacitance and ensures the optimality of the solution, when no capacity constraints are applied. The buffers are then sized and clock nets arerouted to minimize the delay, slope, and skew constraints. We compare the clocktrees obtained by our clustering and the competitive approaches on several blocks from a microprocessor design in 65nm technology. The comparison shows that our algorithm improves the clock tree capacitance consistently by up to 21%.

Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits

Abstract: A balanced tree clock distribution network for an integrated circuit including a branching clock line of layered metal in which each branch of the clock line has equal resistance, apparatus for shielding the clock line on both sides in the same layer of material of the integrated circuit, and apparatus for providing jumpers for crossing the clock line at right angles in a different layer of material of the integrated circuit which jumpers appear at the same preselected distances along each branch of the clock line.

Clock phase correction circuit

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for reducing the size of a jitter by outputting an inner clock in a clock phase correction circuit, outputting a feedback clock, comparing the phases of them, outputting a detection signal, outputting a control signal, inverting an outer clock, receiving the feedback clock and reducing the phase difference. SOLUTION: An outer clock is inputted to a first phase conversion part 51 and the first phase conversion part 51 selects an upper limit to which a feedback clock belongs in four upper limits. Two outputs Out 11 and Out 12 being the references of the upper limit are outputted. Outer clock Extclk and the inverse of Extclk are inputted to the first phase conversion part 51, and it outputs a signal A having the phase of 90 degrees and the signal, the inverse of A, which has the phase of 270 degrees, to a first multiplexer. A second phase conversion part 53 selects the signal A outputted by the first phase conversion part 51 and a signal Out 21 having the intermediate phase of the signal, the inverse of Extclk signal and transmits them to output Out 22.

Dynamically scalable low voltage clock generation system

Abstract: A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock. If any of the scaling dynamics may affect the system clock, then the fixed frequency clock may be selected as the system clock until any transients have stabilized. The MUX may also stop the system in a known logic state. The PLL may also be optimized while the system is running.

Source synchronized metastable free bus

Abstract: The bus of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. In a first embodiment, a high speed clock signal and slower speed clock enable signal are globally distributed from a central arbiter to agents coupled to the bus. A sending agent utilizes the high speed clock signal for source synchronized data transfers by forwarding the high speed clock signal, along with the data, to one or more receiving agents. Thus, the globally distributed clock signal is used to accomplish source synchronized data transfers. Arbitration requests, by contrast, are processed at the slower clock enable signal rate in a globally synchronous fashion. In addition, by communicating data cycles information from the central arbiter to the receiving agent at the slower clock enable signal rate, the present invention avoids resynchronization and the possibility of metastability. Dead time between packets of data is minimized in the present invention by placing the central arbiter in the center of the bus. An alternative embodiment is disclosed wherein a slower speed clock signal is globally distributed to a plurality of agents and a central arbiter. Each agent then generates a high speed clock signal that is divided down and phase locked to the slower speed clock signal, and this high speed clock signal is then utilized for high-speed, source synchronized data transfers. Arbitration and consistency information are handled at the slower speed clock signal rate. In the alternative embodiment, resynchronization is avoided through the use of a header signal.