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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
01 Apr 2004
TL;DR: In this paper, a frequency-voltage mechanism for power management including first and second PLLs, select logic, control logic, and voltage control logic is presented, where power consumption is dynamically adjusted without undue delay while providing significant power efficiency benefits.
Abstract: A frequency-voltage mechanism for power management including first and second PLLs, select logic, control logic, and voltage control logic. The first PLL generates a first source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second source clock signal at a second frequency based on a first frequency control signal and the bus clock signal. The select logic selects between the first and second source clock signals to provide a core clock signal based on a select signal. The clock control logic detects power conditions via at least one power sense signal, provides the first frequency control signal according to power conditions, and provides the select signal. The voltage control logic adjusts the operating voltage commensurate with frequency of the core clock signal. Power consumption is dynamically adjusted without undue delay while providing significant power efficiency benefits.

38 citations

Patent
13 Mar 2012
TL;DR: In this paper, a clock recovery circuit for multi-lane communication systems is presented, where local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined.
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

38 citations

Patent
Lawrence D. Cepuran1
18 Sep 1995
TL;DR: In this paper, the clock signal generator generates a clock signal alternately of at least two frequencies, namely a low frequency and a high frequency, when information is not transmitted upon the bus, and the circuit is operated at the low frequency level.
Abstract: At least two circuit elements are interconnected by a bus which permits transmission of information between the circuit elements. A clock signal generator generates a clock signal alternately of at least two frequencies, namely, a low frequency and a high frequency. When information is not transmitted upon the bus, the clock signal generator generates the clock signal of the low frequency, and the circuit is operated at the low frequency level. When information is generated upon the bus, the clock signal generator generates a clock signal of the high frequency and the circuit is operated at the high frequency. Detection of a start bit, for example, forming a first bit of a word transmitted upon the bus, once detected, causes the clock signal generator to generate the clock signal of the increased frequency. Because the power consumption of an electrical circuit is proportional to the frequency at which the circuit is operated, the circuit is operated at minimal power levels except during times in which information is transmitted.

38 citations

Proceedings Article
01 Jun 2010
TL;DR: In this article, an ECG signal processor (ESP) is proposed for ambulatory arrhythmia monitoring systems, which consists of three heterogeneous processors and performs filtering, data compression, ECG classification and encryption.
Abstract: An ECG signal processor (ESP) is proposed for ambulatory arrhythmia monitoring systems. The ESP consists of three heterogeneous processors and performs filtering, data compression, ECG classification, and encryption. A data reduction scheme, consisting of skeleton and Huffman coding, are employed to reduce the on-chip memory capacity and memory access power. Clock gating and voltage scaling are also applied to reduce the power consumption. The ESP consumes 1.26-µW at 0.7V, while providing real time signal processing.

38 citations

Journal ArticleDOI
TL;DR: This paper presents a novel clustered clock gating to increase power efficiency at architectural level without performance loss and preserving the reusability of the macrocell, using an 8051 core.
Abstract: Power saving is becoming one of the major design drivers in electronic systems embedding microcontroller cores. Known microcontrollers typically save power at the expense of reduced computational capability. With reference to an 8051 core, this paper presents a novel clustered clock gating to increase power efficiency at architectural level without performance loss and preserving the reusability of the macrocell. Different from known clustered-gating strategies where the number of clusters is fixed a priori, the optimal cluster organization is derived, considering both the macrocell complexity and switching activity. When implementing the 8051 core in CMOS technology, the proposed approach leads to a 37% power saving, which is higher than the 29% permitted by automatic-clock-gating insertion in commercial computer-aided design tools or the 10% of state-of-the-art clustered-gating strategies. To assess its full functionality, the power-optimized cell has been proved in silicon that is embedded in an automotive system for sensors interface/control

38 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884