Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio

Abstract: A method of transmitting a signal from a first clock domain (96) to a second clock domain (92) commences with the generation of first clock and second clock signals (63, 65). The first and second clock signals (64, 62) are substantially synchronous and have respective frequencies that are non integers multiples. A first signal which is generated in the first clock domain (96) responsive to transition of the first clock signal (64) that is substantially coincident with a transition of the second clock signal (62), is prevented from being latched in the second clock domain (92) responsive to the transition of the second clock signal (62). The first clock signal (64) is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals (64, 62).

Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

Abstract: A duty cycle correction circuit is configured to adjust the duty cycle of a clock signal in a clock distribution network. The duty cycle correction circuit adjusts the duty cycle of the clock signal by adjusting the transitional delay in a single edge of each clock pulse of the clock signal without interrupting the other edge of each clock pulse of the clock signal. This feature enables the duty cycle correction circuit to adjust the duty cycle of the clock signal without interrupting the operation of a phase-locked loop (PLL) used in the clock distribution network. The duty cycle correction circuit includes a delay-control circuit coupled to a clock-inverter circuit. The delay-control circuit generates a delay-control voltage, which is provided to the clock-inverter circuit to control the transitional delay in a single edge of each clock pulse of the clock signal.

Digital ground bounce reduction by supply current shaping and clock frequency Modulation

Abstract: In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

Adaptive clock recovery in asynchronous transfer mode networks

Abstract: In a data communication network, a system clock rate can be inferred at a receiver by measuring the data rate during successive periods. This information is used to adjust or adapt a receiver output clock to the inferred system clock. To adapt a receiver buffer output clock frequency to the buffer input clock frequency, the level of the buffer is periodically monitored. If the fill level is greater than an upper threshold, the output clock frequency is incremented. If the fill level is less than a lower threshold, the output clock frequency is decremented. A count is maintained of the number of successive adjustment operations performed while the fill level is outside the range bounded by the thresholds. When the fill level returns to the bounded range, a number of reverse frequency adjustments are performed. The number of reverse frequency adjustments are less than the number of earlier opposite frequency adjustments, preferably by a factor of two. The reverse corrections converge the output clock frequency toward the input clock frequency, reducing oscillations.

Divide by three clock divider with symmetrical output

Abstract: A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.