Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Clock generator control circuit

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Low power and low timing jitter phase-lock loop and method

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

Abstract: We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal VDD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery (VDD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at VDD = 1.2 V, it dissipates 186 μW.

Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference

Abstract: An integrated circuit includes clock synthesis and distribution circuitry that includes cascaded PLLs to deliver low-noise transmit and receive clock signals that can be tuned over a broad range of frequencies. The clock synthesis circuitry derives a low-jitter intermediate reference clock signal IRClk from a relatively noisy, low-frequency external reference clock signal using a first PLL stage with a high-Q voltage-controlled oscillator (VCO). This first PLL stage has a low loop bandwidth, and thus acts as a low-pass filter (LPF) to remove the reference clock jitter. The low jitter intermediate clock signal is distributed to one or more second PLL stages that derive higher frequency transmit and/or receive clock signals from the intermediate clock signal. Each second PLL stage includes a low-Q VCO that exhibits a considerable tuning range to support a number of transmit and receive data rates. The second PLL stages are adapted to provide high loop bandwidth to minimize phase noise introduced by the low-Q VCO.

Clock loss detection and switchover circuit

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.