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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
07 Sep 2004
TL;DR: In this paper, an integrated circuit comprising at least one active device that outputs light during a change in state of the at least other active device during operation, and a clock circuit configured to output a clock signal to each active device, the clock signal rate being varied so as to hinder optical detection of a pattern of the light during operation of the active device.
Abstract: An integrated circuit comprising: at least one active device that outputs light during a change in state of the at least one device during operation; a clock circuit configured to output a clock signal to the at least one active device, the clock signal rate being varied so as to hinder optical detection of a pattern of the light during operation of the at least one active device.

36 citations

Patent
11 Jan 1996
TL;DR: In this paper, a clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein.
Abstract: The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

36 citations

Patent
10 Sep 2002
TL;DR: In this article, a robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator, and the contents of nonvolatile register are read to select the clock source for the circuit.
Abstract: Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the circuit. Upon successful selection and clean up of system clock, the reset is removed.

36 citations

Patent
19 Jul 2001
TL;DR: In this paper, a DLL circuit includes a replica delay time adjusting section and a phase control section, which adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of a data output buffer.
Abstract: A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.

36 citations

Patent
19 May 2000
TL;DR: In this paper, a bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates an operation packing signal when common operations are ready to issue.
Abstract: Circuitry reduces power consumption by a microprocessor with operand-value-based clock gating. A bit detect unit detects the condition of a pre-determined number of bits of an operand. If the pre-determined number of bits are not necessary for executing the operand, a condition detect signal is generated. Gating logic receives the condition detect signal and initiates a gated clock signal. Latching circuitry or pre-charge circuitry receives the gated clock signal and disables the pre-determined number of bits, preventing the execution of unnecessary bits by the microprocessor and reducing the power consumed during execution. Operation packing improves microprocessor performance by packing narrow-width operations for parallel execution by the microprocessor. A bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates a condition detect signal. Issue logic detects common operations within execution instructions and receives the condition detect signal, initiating an operation packing signal when common operations are ready to issue and the operands involved contain a pre-determined number of bits unnecessary for execution. Multiplexers receive the operation packing signal and move data from the lowermost bits of the operands to the upper sub-words of the source operand bus, creating a parallel sub-word operation. After execution, multiplexers move data from upper sub-words of the result onto the lowermost bit boundaries of the individual result operands.

36 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884