Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Digital pll circuit and clock generating method

Abstract: PROBLEM TO BE SOLVED: To eliminate noise from the outside or from a power supply and realize a stable phase clock output by obtaining a clock synchronized with a reference signal phase by a second PLL circuit and obtaining a clock phase- compared by a first PLL circuit between this reference signal. SOLUTION: In the first PLL circuit 51, a phase comparing circuit 2 compares the periods and phase of the oscillation clock 101 of an X'tal oscillation circuit 1 and a phase comparing signal 109 outputted by a 1/N frequency dividing circuit 5 with each other. When the period of the signal 109 is faster or slower, the oscillation frequency of a voltage controlled oscillator VCO 4 is controlled to make a reference clock 103 to send to a signal switching circuit 8. A phase comparing circuit 6 compares an inputted horizontally synchronizing signal 102 to the second PLL circuit 52 and the output 108 of a 1/M frequency dividing circuit 9 with each other, filters its result by a digital filter 7 to control a signal switching circuit 8 to switch a phase matching signal in the plural clocks 103 to output a system clock 104 of reduced jitters. COPYRIGHT: (C)1999,JPO

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating

Abstract: Nonbinary LDPC (NB-LDPC) codes, defined over Galois field, offer better coding gain and a lower error floor than binary LDPC codes. However, the complex decoding and large memory requirement have prevented any practical chip implementations. We present a 1.22 Gb/s fully parallel decoder of a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS. The reduced number of edges in NB-LDPC code's factor graph permits a low wiring overhead in the fully parallel architecture. The throughput is further improved by a one-step look-ahead check node design that increases the clock frequency to 700 MHz, and the interleaving of variable node and check node operations that shortens one decoding iteration to 47 clock cycles. We allow each processing node to detect its own convergence and apply dynamic clock gating to save power. When all processing nodes have been clock gated, the decoder terminates and continues with the next input to increase the throughput to 1.22 Gb/s. The dynamic clock gating and decoder termination improve the energy efficiency to 3.03 nJ/b, or 259 pJ/b/iteration, at 1.0 V and 700 MHz. Voltage scaling to 675 mV improves the energy efficiency to 89 pJ/b/iteration for a throughput of 698 Mb/s at 400 MHz.

Clock adjustment method and apparatus for synchronous data communications

Abstract: The disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system. The transmitter clock is periodically compared with a common reference clock and a fixed increment clock adjustment signal is transmitted to the receiver which adjusts its clock by applying the fixed increment clock adjustment signal to the common reference clock. The utilization of a predetermined fixed increment clock phase adjustment signal eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.

Synchronous pipeline with normally transparent pipeline stages

Abstract: A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.

Low power clock circuit

Abstract: High-efficiency clock generator (10) circuits are disclosed having single or complementary outputs (Q) for driving capacitive loads (11). The clock generator has therein at least one pair of complementary FET switches (14,15) coupled between the output of the generator and power supply rails, and an inductor (13). The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.