Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Abstract: Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthesis. Local clock skew (LCS) is the clock skew between any two sinks with distance less than or equal to a given threshold. It is defined in the ISPD 2010 High Performance Clock Network Synthesis Contest [1], and it is a novel criterion that captures process variation effects on a clock network. In this paper, we propose a hybrid method that creates a mesh upon a tree topology. Total wire and buffer capacitance is minimized under the LCS and slew constraints. In our method, a clock mesh will be built first according to the positions and capacitance of the sinks. A top-level tree is then built to drive the mesh. A blockage-aware routing method is used during the tree construction. Experimental results show our efficiency and the solution generated by our approach can satisfy the LCS constraint of all the benchmarks in the contest [1], with a fair capacitance usage.

Phase shift correction circuit for monolithic random access memory

Abstract: A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).

Clock scheme for VLSI systems

Abstract: An integrated circuit includes an input clock generator circuit (10) responsive to an external TTL level clock signal (C1) for generating an internal CMOS level system clock signal (C2) for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit (16) responsive to either the internal CMOS level system clock signal (C2) or an external CMOS level system clock signal (C3) for generating internal CMOS level phase clock signals (0₁, 0₂) for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.

Clock distribution in general VLSI circuits

Abstract: Minimization of clock skew in VLSI circuits to within a tolerable range is important for dependable operation of any digital system. Moreover, excessive delay through a clock distribution network can significantly degrade the performance of the digital system. Differences in path lengths and active elements of a clock distribution network are largely responsible for clock skew while excessive delay is a result of very long signal routes in the network. Improved integrated circuit processes are placing an increasing demand on current clock routing schemes through higher clock rates and larger die sizes. This paper proposes a clock routing scheme that primarily minimizes clock skew in a general VLSI circuit whose functional elements may be of various sizes and placements. A secondary objective is to reduce the overall network delay. The clock distribution network is generated based on the analysis of RC trees. In the networks so generated, the delay seen from the clock entry point of a circuit to all modules within the circuit is nearly identical. In constructing the clock distribution networks, the fan out of a buffer is accounted for and flexibility in placement of buffers is utilized. >

Two-dimensional signal gating for low-power array multiplier design

Abstract: Two-dimensional (2-D) signal gating schemes are proposed for low-power array multiplier design. 2-D gating provides gating lines for both multiplicand and multiplier operands. Different regions of the multiplier are dynamically deactivated according to the actual precision of each operand. Bit-level implementation is studied in order to minimize the gating overhead and make a realistic evaluation. Compared to previous work, the 2-D signal gating is better in terms of power consumption, power-delay product and power-area product.