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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
16 May 2000
TL;DR: In this article, a synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation, and data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc.
Abstract: A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

136 citations

Patent
09 Apr 1999
TL;DR: In this paper, a delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal, which is received on a feedback input terminal of the delayed lock loop.
Abstract: A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.

136 citations

Patent
20 Jul 1984
TL;DR: In this article, a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuits composed of C-MOS gates for further reducing the power consumption is presented.
Abstract: Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

134 citations

Journal ArticleDOI
TL;DR: In this article, a resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described.
Abstract: A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.

134 citations

Patent
12 Feb 1996
TL;DR: In this paper, an integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines.
Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.

133 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884