Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Clock buffer polarity assignment for power noise reduction

Abstract: Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively.

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS

Abstract: High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 – 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between clock and data, jitter tolerance is improved by tracking jitter up to f bit /4L [2]. If the mismatch is 5UI, at 4Gb/s and 8Gb/s the clock path jitter tracking bandwidth (JTB) should be 200MHz and 400MHz respectively. In summary, the clock path in a clock forwarded transceiver should provide flexible clock multiplication, a controlled phase shift, and a JTB adjustable over 100's of MHz to accommodate different channel losses, bit rates, and path delay mismatches.

Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors

Abstract: An asynchronous validity checking system and method is disclosed for monitoring a plurality of clock signals carried on separate electrical conductors to assure continuing transitions of each clock signal. A master clock is utilized to produce a plurality of phase-related clock signals on the separate electrical conductors, and the transitions of the clock signals are sensed on each electrical conductor adjacent to the distribution point to a controlled unit to assure that all clock signals are continuously operational. The validity checking system includes a locking synchronizer having a plurality of flip-flops each of which receives a different one of the clock signals and a timing signal from a timing oscillator that is independent of, and asynchronous with respect to, the clock signals from the master oscillator with the clock signals being locked into the flip-flops on the rising leading edges of the pulses of the timing signal. A sequence and presence checking unit receives the output signals from the flip-flops and produces reset pulses which are coupled to digital counters incremented by the falling trailing edges of counter clock pulses that are frequency related to the timing signal pulses coupled to the locking synchronizer. As long as transitions of the clock signals are sensed on each of the electrical conductors to reset the counters within a predetermined period of time, no fault indication is produced. If a transition is not sensed, however, the counters are not reset within the predetermined period of time and a fault indication is produced that is indicative of a defect in a clock signal. Upon sensing of the failure of a transition of a clock signal, a fault indication is produced which may be utilized to automatically effectively stop the clock, selectively switch power off, or switch the master clock from a controlled unit, such as a magnetic recording device, to prevent damage and/or information loss.

Constrained clock shifting for field programmable gate arrays

Abstract: Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting optimization techniques to improve the clock frequency as a post place and route step.Clock Shifting Optimization is a technique first formalized in [4]. It is a cycle-stealing algorithm that allows one to reduce the critical path delay of a synchronous circuit by shifting the clock signals at each register. This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register. Typical FPGAs contain a number of special purpose global clock networks that distribute clock signals to every register in the chip. Unused global clock lines in FPGAs can be used to distribute a finite set of clock skews to the entire circuit. We propose an efficient integer programming method to find the optimal circuit improvement for a finite set of clock skews. This technique is modified to consider inherent uncertainties present in the timing models. The uncertainty controls the aggressiveness of the optimizations as we must take great care in ensuring functionality for any range of possible timing characteristics.Our results confirm intuition that more aggressive speed optimizations can be performed as timing models become more accurate. We also show that providing 4 skewed versions of the nominal clock signal results in the best delay--area tradeoff. This result is evocative as it may suggest future FPGA architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater power requirements from increased clock network flexibility.

Digital design component with scan clock generation

Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.