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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
Jinil Chung1, Hoon Choi1
30 Jun 2006
TL;DR: In this article, a delay-locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first external clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device.
Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.

33 citations

Proceedings ArticleDOI
08 Apr 1999
TL;DR: This research provides a clock power model for SoC that takes into account the impact of architectural, design, and logic style on clock power and will be used in designing the clock network and estimating its power dissipation.
Abstract: The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

33 citations

Patent
05 Sep 1995
TL;DR: In this article, the first and second communication devices respectively include clock selection circuits and clock production circuits for producing a synchronous clock from the selected clock, respectively, and supply the chosen clock to the other communication device which is a mating-side device.
Abstract: A sharp phase variation of a clock is suppressed when master/slave status of a first and second communication device is changed over. The first and second communication devices respectively include clock selection circuits and clock production circuits for producing a synchronous clock from the selected clock, respectively, and supply the selected clock as the synchronous clock to the other communication device which is a mating-side device. One of the first and the second communication devices is a reference selection side and becomes a slave side, and the other device is a mating synchronous clock selection side and becomes a master side. Respective data signals from the communication devices are bit multiplexed in a multiplexing device on the basis of the synchronous clock. The first communication device includes a delay circuit for delaying the mating-side synchronous clock by a phase difference between a clock transmitted from the selection circuit through the clock production circuit and a clock transmitted in the mating-side device from the selection circuit through the selection circuit and the clock production circuit. In this manner, both clocks inputted into the selection circuits are made synchronous by the delay processing, so that a sharp phase variation at the master/slave changeover is suppressed and the multiplexed output from the multiplexing device remains virtually undisturbed during a master/slave change over event.

33 citations

Patent
13 Aug 1986
TL;DR: In this paper, a clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer is presented.
Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.

33 citations

Patent
26 Sep 2013
TL;DR: In this article, an integrated circuit (IC) with a phase locked loop with capability of fast locking is described, which comprises: a node to provide a reference clock, a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the dividers, and operability to release reset in synchronization with the reference clock.
Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

33 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884