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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
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Proceedings ArticleDOI
10 Feb 1998
TL;DR: An automated layout design technique for the gated-clock design that could be less than 0.2 ns keeping timing constraints for enable-logic parts.
Abstract: This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

33 citations

Patent
25 Apr 2007
TL;DR: In this paper, the clock circuit is coupled to produce a first clock signal when the SOC is in low power mode and a second clock signal in a performance mode, where the first clock signals are less accurate than the second clock signals.
Abstract: A system on a chip includes a processing module, ROM, RAM, and a clocking circuit. The clock circuit is coupled to produce a first clock signal when the SOC is in a low power mode and to produce a second clock signal when the SOC is in a performance mode, where the first clock signal is less accurate than the second clock signal. The clock circuit consumes more power when producing the second clock signal than when producing the first clock signal.

33 citations

Proceedings ArticleDOI
Jindrich Zejda1, Paul Frain1
10 Nov 2002
TL;DR: A new theoretical framework is proposed that allows to apply known graph algorithms instead of time consuming forward and backward multi-pass tracing algorithms and heuristics that are limited to some network topologies and thus is helping hundreds of designers to achieve faster clock speeds of their chips.
Abstract: The paper presents a simple yet powerful general theoretical framework and efficient implementation for removal of clock network timing pessimism. We address pessimism in static timing analysis (STA) tools caused by considering delay variation along common segments of clock paths. The STA tools compute setup (hold) timing slack based on conservative combinations of late (early) launching and early (late) capturing arrival times. To avoid exponential-time path-based analysis the STA tools use both early and late arrival times on gates common to both launching and capturing paths. It is impossible in real circuit and is observed as the clock network pessimism in STA. Our approach supports any kind of delay variation though the typical causes of the pessimism are process, voltage, and temperature on-chip variation, and reconvergence in clock network. We propose a new theoretical framework that allows to apply known graph algorithms instead of time consuming forward and backward multi-pass tracing algorithms and heuristics that are limited to some network topologies [4]. The new graph-based framework supports clock networks of virtually any size and type, e.g., tree, mesh, hybrid, clock gating, chains of multipliers and dividers, loops in such chains, etc. The implementation based on the proposed framework has proven its strength in a commercial sign-off static timing analyzer and thus is helping hundreds of designers to achieve faster clock speeds of their chips.

33 citations

Patent
Masaaki Shimooka1
10 Oct 2007
TL;DR: In this paper, a semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to save an internal node data in a memory in a save mode.
Abstract: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node data in a memory in a save mode; and a backup control circuit configured to supply to the target circuit, a system clock signal in the normal mode, a test clock signal in the scan path test mode, and a save/recover clock signal in the save mode, and to control the target circuit and the memory such operations in the normal mode, the scan path test mode, and the save mode are performed. The test clock signal is slower than the system clock signal, and the save/recover clock signal is slower than the system clock signal and faster than the test clock signal.

33 citations

Proceedings ArticleDOI
08 Nov 1992
TL;DR: An algorithm, based on max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer is presented, and the results are promising.
Abstract: In the design of high speed digital VLSI circuits, it is preferable that the clock net be routed on the metal layer with the smallest RC delay. This strategy not only avoids the difficulties of having different electrical parameters on different layers, but also eliminates the delay and attenuation of the clock signal through vias. The clock phase-delay is also decreased. An algorithm, based on max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer is presented. The clock tree achieves equal path lengths, i.e., the lengths of the paths from the clock source to each clock terminal are exactly the same. In addition, the path length from the source to clock terminals is minimized. Some examples including industrial benchmarks have been tested, and the results are promising. >

33 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884