Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Phase locked loop clock generator

Abstract: A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.

Dual loop delay-locked loop

Abstract: A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop (418) and a phase acquisition loop (420). The frequency acquisition loop delays the reference clock (REF-CLK) to produce an intermediate clock (FCLK', BCLK') which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock (LOC-CLK) to produce a local clock synchronized to the reference clock. The frequency acquisition loop (418) comprises a first delay circuit (400) adapted to delay the reference clock (REF-CLK) by an adjustable delay period which is selected from a plurality of non-adjustable delay periods by a first delay controller (404). The latter preferably comprises a cross-sensing phase detector pair (504) and a control logic (506). The phase acquisition loop (420) comprises a second delay circuit (402) adapted to delay the intermediate clock (FCLK', BCLK') by an adjustable delay period by a second delay controller (406). The latter may comprise a phase detector, a charge pump and a loop filter.

A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

Abstract: A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7/spl times/ frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110/spl deg/C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300/spl mu/W at clock gate-off, zero-cycle response during clock re-enable, and <4% static phase error.

A clock-tuning circuit for system-on-chip

Abstract: System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache

Abstract: The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for <11ps global clock skew in a 435mm2 die. The cache and control sections contain 2 primary clock domains and 11 clock spines. A pipelined de-skew logic tolerant to inter-domain clock uncertainties manages the core and cache/control data communication