Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Decoupled scan path interface

Abstract: An interface to internal scan paths within an IC for synchronizing a test clock and a system clock without adversely affecting their operation. The test clock provides input test data (TDI) to the interface and receives output test data (TDO) from the interface at the test clock rate. The system clock drives the test data through the scan path at the system clock rate. The two clocks are "decoupled" in that they run independently, being synchronized by the interface for clocking the test data into, through and out of the scan path. In effect, the interface decouples the internal scan paths driven by the system clock from the test logic driven by the test clock. This feature enables the IC to be tested "at speed" and provides for synchronization between the test clock and system clock over a wide range of test clock frequencies.

Method for detecting clock failure and switching to backup clock

Abstract: A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

Low power flip-flop circuit and method thereof

Abstract: A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

Method and apparatus for clock gating clock trees to reduce power dissipation

Abstract: A clock gating circuit reduces the power dissipation in a digital circuit including at least one functional block by gating the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives a clock signal and a clock disable signal generated by the functional block, and gates the clock signal at the input to the clock tree feeding the functional block. Further, a global signal generator is provided to transmit a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.

CPU power supply impedance profile measurement using FFT and clock gating

Abstract: CPU bypass mode clock gating and oscilloscope FFT features enable accurate measurement of a CPU's power delivery network impedance profile. The method described is self checking. Impedance profile characterization up to 100MHz is demonstrated.