Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Low-power scan design using first-level supply gating

Abstract: Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.

Integrated power clock generators for low energy logic

Abstract: Low-energy (adiabatic) logic families have been proposed to reduce energy consumption of VLSI logic devices. Instead of the conventional DC power supply, these logic families require AC power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic. This results in better system efficiency and simpler power distribution. Closed-form results are derived to facilitate efficiency-optimized design of the proposed power clock generators. To illustrate system integration and energy savings, the optimized power clock is used to supply a novel clocked CMOS adiabatic logic (CAL). >

System and method for dynamic clock generation

Abstract: An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are “resources.” The devices that access the resources are “controllers.” The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table. The adder sums the contents of the bandwidth registers of the controllers that are accessing a resource. The sum is an index to an entry in a frequency table. The value held in the frequency table is applied to the selection inputs of the MUX to select the clock for the resource. If no controllers are requesting access to the memory controller, the clock controller shuts down the memory clock. Accordingly, the clock frequency of the resource is determined by the bandwidth utilization of the controllers requesting access to the resource.

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Abstract: A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-/spl mu/m CMOS with double-well and triple-metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

Frequency and voltage scaling architecture

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.