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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Proceedings ArticleDOI
11 May 2005
TL;DR: This paper has developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from a layout specification of a rotary clock design and is able to accurately estimate the frequency and power dissipation of the rotary Clock design using SPICE simulations.
Abstract: Rotary clock is a multi-gigahertz clock distribution technique based on the principle of wave propagation in transmission lines. In this paper, we perform the first quantitative investigation on the power dissipation of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from a layout specification of a rotary clock design. As a result, we are able to accurately estimate the frequency and power dissipation of the rotary clock design using SPICE simulations. Using our tool, we have uncovered the key power dissipation mechanisms of rotary clock and proposed several power reduction strategies. Furthermore, our power analysis has revealed that rotary clock designs can achieve power savings of up to 70% in comparison with conventional clock tree implementations.

31 citations

Patent
Won-Joo Yun1, Hyun-woo Lee1
22 Feb 2007
TL;DR: In this article, a delay-locked loop (DLL) is proposed to compensate for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.
Abstract: A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

31 citations

Proceedings ArticleDOI
08 Jun 2008
TL;DR: A new method is introduced for automatically synthesizing conditions under which the transition of a register may be safely blocked in a way that minimizes netlist perturbation and is both timing- and physical-aware.
Abstract: Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.

31 citations

Patent
19 Jun 1997
TL;DR: In this paper, a phase-locked loop (PLL) circuit is used to power down a microprocessor in a computer system, where the phase lock loop generates bus clock signals for clocking the operations on the bus and core clock signals to clock the core of the processor in response to global clock signal of the computer system.
Abstract: A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.

31 citations

Patent
17 Nov 1997
TL;DR: In this paper, a clock frequency detector is employed in a SDRAM to detect whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate.
Abstract: The present invention employs a clock frequency detector in a SDRAM that detects whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate. In response to the input clock frequency, the clock frequency detector outputs a selection signal to control logic circuitry in the SDRAM indicating whether the SDRAM should operate in either a fast or slow mode. The clock frequency detector employs a frequency detector that detects the frequency of the input clock signal. Based on the frequency of the input clock signal, a selector circuit outputs either a fast or slow selection signal to the control logic circuitry. In response to the fast selection signal, the control logic circuitry performs data access commands at a fast rate, while in response to the slow selection signal, the control logic circuitry executes such commands at a slower, more conservative rate. As a result, the SDRAM device can operate according to its maximum specifications in connection with a fast input clock rate (allowing essentially no margins for error), or perform at a slower rate based on a slower input clock frequency (allowing for some margin of error).

31 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884