Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

System and technique for power management of a universal asynchronous receiver/transmitter by automatic clock gating

Abstract: A clock control unit is provided that controls the gating of a clock signal received by an internal baud generator of a universal asynchronous receiver/transmitter (UART) circuit during an active mode. The clock control unit monitors the UART circuit to determine whether the UART is currently idle. If the clock control unit determines that the UART is idle, the clock signal is gated by a synchronous clock gate circuit. Accordingly, the clock signal is not provided to the baud generator, and a corresponding baud rate signal that normally clocks the receiver state machine of the UART is not generated. Power consumption of the UART is thereby significantly reduced. When a certain predetermined system activity is thereafter detected by the clock control unit that indicates a need for activation of the UART, the clock control unit asserts a clock enable signal that causes the synchronous clock gate circuit to pass the clock signal to an input of the baud generator. In one embodiment, the clock control unit causes the clock signal to be degated if the receipt of serial data is detected at the serial input line of the UART, if the receiver state machine is currently active, if the receiver FIFO and buffer register is not empty, if the transmitter FIFO and holding register is not empty, or if the transmitter state machine is active.

Clock mesh synthesis with gated local trees and activity driven register clustering

Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Clock signal deskewing system

Abstract: A system (10) for distributing synchronized clock signals to spatially distributed circuits (15) includes a pair of transmission lines (16, 18) between first (14) and second (24) sites. Deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit (DELAY) in each deskewing circuit detects the outgoing clock signal on the first line and produceds a local clock signal (CLKL) that lags the outgoing clock signal by an adjustable delay. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar delay to produce a local reference signal. A phase lock controller (30) in each deskewing circuit adjusts the delay of the delay circuits so that the local reference signal is phase locked to the returning clock signal on the second line. When reference signals in all deskewing circuits are phase locked to the returning clock signal, their local clock signals have similar phases.

Skew sensitivity minimization of buffered clock tree

Abstract: Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduces the interconnect length. For a given clock tree of n points and a library of s different buffer sizes, the run time of the presented algorithm is O(log3n•s2).Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm.

Clock Gating and Negative Edge Triggering for Energy Recovery Clock

Abstract: Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions. In this paper, we propose a clock gating solution for energy recovery clocking by gating the flip-flops. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by 1000times in the idle mode with negligible power and delay overhead in the active mode. Applying the proposed clock gating technique to a system of 1000 flip-flops with idle mode probability and data switching activity of 50%, reduces the total power by 47%. We also propose a negative edge triggering solution for the energy recovery clocked flip-flops.