Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

High performance clock distribution for CMOS ASICs

Abstract: An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed

Clock domain crossing fifo

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs

Abstract: Power consumption is dramatically increasing for Static Random Access Memory Field Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new CAD tools are needed. Clock-gating methodologies have been applied in low power FPGA designs with only minor success in reducing the total average power consumption. In this paper, we developed a new structural clock-gating technique based on internal partial reconfiguration and topological modifications. The solution is based on the dynamic partial reconfiguration of the configuration memory frames related to the clock routing resources. For a set of design cases, figures of static and dynamic power consumption were obtained. The analyses have been performed on a synchronous FIFO and on a r-VEX VLIW processor. The experimental results shown that the efficiency in the total average power consumptions ranges from about 28% to 39% with respect to standard clock-gating approaches. Besides, the proposed method is not intrusive, and presents a very limited cost in term of area overhead.

A 660- W 50-Mops 1-V DSP for a Hearing Aid Chip Set

Abstract: This article presents the flow and techniques used to design a low-power digital signal processor chip used in a hearing aid system implementing multiband compression in 20 bands, pat- tern recognition, adaptive filtering, and finescale noise cancella- tion. The pad limited 20 mm chip contains 1.3 M transistors and operates at 2.5 MHz under 1.05-V supply voltage. Under these con- ditions, the DSP consumes 660 W and performs 50 million 22-bit operations per second, therefore achieving 0.013 mW/Mops (milli- watts per million operations), which is a factor of seven better than prior results achieved in this field. The chip has been manufactured using a 0.25- m 5-metal 1-poly process with normal threshold volt- ages. This low-power application-specific integrated circuit (ASIC) relies on an automated algorithm to silicon flow, low-voltage oper- ation, massive clock gating, LP/LV libraries, and low-power-ori- ented architectural choices.

Method and apparatus for a testable high frequency synchronizer

Abstract: A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.