Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs

Abstract: Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.

Method and apparatus for implementing IEEE 1149.1 compliant boundary scan

Abstract: A method and apparatus for pipelining clock control signals across a chip The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip A relatively low speed testing mechanism may be used to drive the testing of the chip externally The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 11491 boundary scan standard

Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer

Abstract: A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

Deskewing global clock skew using localized DLLs

Abstract: An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

System and method for timing abstraction of digital logic circuits

Abstract: A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.