Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Method and apparatus to reduce clock jitter of an on-chip clock signal

Abstract: An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.

Data path clock skew management in a dynamic power management environment

Abstract: A clock gating apparatus that is cost efficient and allows power conservation is presented. The clock gating apparatus is implemented to allow data paths, that are used to process data, to be enabled or disabled as desired while preventing the clock-skew problem. The clock gating apparatus includes a plurality of clock gating circuits, wherein one clock gating circuit is implemented for each data path. In a first embodiment, while all the data paths propagate data in a first direction and eventually merge together at a node, the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction. In a second embodiment, parallel data paths that are mutually exclusive of each other propagate data in a first direction and the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction.

A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000

Abstract: For JPEG 2000-based multimedia systems, embedded block coding with optimized truncation (EBCOT) tier-1 has become a bottleneck for the entire system. EBCOT tier-1 is full with bit operation, so hardware implementation is more efficient in both system throughput and power consumption. In this paper, a three-level parallel high-speed power-efficient architecture for EBCOT tier-1 is proposed. This architecture is divided into bit-plane coding (BC), arithmetic encoding (AE), and first-in first-out (FIFO) that connects BC with AE and balances the different throughput between them. To improve the system throughput, three levels of parallelism in BC are adopted: 1) the parallelism among bit planes; 2) the parallelism among three pass scans; and 3) the parallelism among coding bits. AE is implemented in four pipeline stages. To achieve power efficiency, several techniques are applied: in BC, simple control logics are added to reduce computation in BC; in FIFO, memory access is reduced since AE is fed with fixed values instead of reading from FIFO; in AE, simple control logics are added to reduce computation in AE and forwarding technique combined with clock gating is adopted to reduce switching activities in the last two pipeline stages. The proposed architecture can encode one code block with size NtimesN in only around (0.35~0.46)timesNtimesN clock cycles. Experimental results, with standard test image benchmarks, show that the proposed power reduction techniques keep the same system throughput and achieve about 27% improvement in the power consumption by comparison with the architecture without these techniques

Method and apparatus for eliminating clock jitter in continuous-time Delta-Sigma analog-to-digital converters

Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter (17) that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter (17) preferably includes at least two switches and a capacitor (28).

Impact of Thermal Gradients on Clock Skew and Testing

Abstract: In this article, we analyze the impact of within-die thermal gradients on clock skew, considering temperature's effect on active devices and the interconnect system. This effect, along with the fact that the test-induced thermal map can differ from the normal-mode thermal map, motivates the need for a careful consideration of the impact of temperature gradients on delay during test. After our analysis, we propose a dual-VDD clocking strategy that reduces temperature-related clock skew effects during test. Clock network design is a critical task in developing high-performance circuits because circuit performance and functionality depend directly on this subsystem's performance. When distributing the clock signal over the chip, clock edges might reach various circuit registers at different times. The difference in clock arrival time between the first and last registers receiving the signal is called clock skew. With tens of millions of transistors integrated on the chip, distributing the clock signal with near-zero skew introduces important constraints in the clock distribution network's physical implementation and affects overall circuit power and area