Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Symmetric clock synchronization in sensor networks

Abstract: In this paper we argue that achieving symmetric errors is the key to an improved understanding of clock synchronization. We present a clock synchronization algorithm with drift compensation that implements this symmetric error paradigm. The performance of the algorithm is evaluated by measurements in an indoor testbed using the TinyNode hardware platform. We show that the remaining error is symmetric and in the range of the clock granularity.

Clock gating for power optimization in ASIC design cycle theory & practice

Abstract: In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.

Spread spectrum clock generator and integrated circuit device using the spread spectrum clock generators

Abstract: The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ΔΣ quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.

A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture

Abstract: An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s/spl times/8-channel receiver fabricated with 0.13-/spl mu/m CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm/sup 2/. It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within /spl plusmn/5.

Clock skew measurement circuit on a microprocessor die

Abstract: A structure and related method for determining the uncertainty window associated with clock signals on a microprocessor using circuitry on the microprocessor die itself and external software. A target clock signal of interest is compared to a series of reference clock signals having the same frequency, but differing in phase relationship. Where the target clock signal makes state transitions with respect to the various reference clock signals over the course of several thousand comparisons is indicative of the uncertainty window for that target clock. By adjusting the phase relationship between the reference clock signals, and thereby adjusting the width of the time windows defined by corresponding features of the reference clock signals, the uncertainty window for the target clock signal may be iteratively determined.