Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Synchronization of a low power oscillator with a reference oscillator in a wireless communication device utilizing slotted paging

Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

Low power techniques for Motion Estimation hardware

Abstract: Motion Estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex II FPGA using Xilinx XPower tool. Glitch reduction and clock gating together achieved an average of 21% dynamic power reduction. The proposed technique achieved an average of 23% dynamic power reduction with an average of 0.4db PSNR loss. The proposed technique achieves better power reduction than pixel truncation technique with a similar PSNR loss.

Duty cycle correction circuit with frequency-dependent bias generator

Abstract: A duty cycle correction circuit operates by alternately speeding and slowing successive transitions of an input clock signal. By altering the rising and falling edge rates of a clock signal asymmetrically, the duty cycle of the clock signal is adjusted without shifting the DC level of the clock signal. In one embodiment, the duty cycle correction circuit includes current sources in place of resistive loads to avoid shifting the DC level of output clock signals. Frequency-dependent current sources that generate increased bias currents at higher frequency are used to achieve duty cycle correction over a broad range of input frequencies.

All-Optical Clock Recovery for NRZ-DPSK Signals

Abstract: We experimentally demonstrate an optical clock recovery scheme for nonreturn-to-zero differential phase shifting keying (NRZ-DPSK) data. By using an optical circuit made by a proper fiber Bragg filter and a Fabry-Peacuterot based clock extraction circuit, we obtain a stable and low jitter 10-GHz optical clock signal. This signal shows comparable performance with the original electrical clock in bit-error-rate measurements and oscilloscope triggering operation

Circuit for glitch-free switching of asynchronous clock sources

Abstract: A circuit, including a state machine, e. g. a logic array and a set of controlled storage devices, receives conditioning signals, such as reset, power failure signals and signals fed back from the storage devices, and uses the signals to determine which of a number of clock sources is to be used in a system. The state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches. The circuit's output signal controls a number of AND gates, each of which gates a particular clock signal to an output line. When a power fail condition occurs, a switch between a first clock signal and a substantially lower frequency clock signal is required to conserve power. This is achieved by first switching to a synchronized lower frequency clock signal, and then to a non-synchronized lower frequency clock signal when the first clock signal is switched off since the synchronized low frequency clock signal is lost at this time when the clock source from which the first signal is generated is switched off to conserve power. A reverse process switches back to the high frequency clock without glitches when power returns.