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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
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Patent
07 Sep 2004
TL;DR: In this article, a method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed, where a developed tool can be embedded in the existing clock tree synthesization design flow to ensure satisfying both specifying database constrains and clock skew constraints.
Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

28 citations

Patent
17 Feb 2010
TL;DR: In this paper, a clock data recovery circuit including a first phase detector, a loop filter, a charge pump, a voltage-controlled oscillator, and a second phase detector is described.
Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

28 citations

Patent
Kim Seok Jin1
14 May 1998
TL;DR: In this paper, a clock forwarding circuit of a semiconductor integrated circuit which increases an operation timing margin of a data receive port and reduces power consumption is presented, where a self-generated receive clock signal is generated from a delayed send clock transmitted from a data send port via the data line.
Abstract: A clock forwarding circuit of a semiconductor integrated circuit which increases an operation timing margin of a data receive port and reduces power consumption, and a clock forwarding method, are provided. In the clock forwarding circuit for performing the clock forwarding method, upon abnormal operation of the semiconductor integrated circuit, such as during power-up or initialization, the data receive port captures the amount of interconnection delay of a data line and generates a receive clock signal which is self-generated, from a delayed send clock transmitted from a data send port via the data line. On the other hand, when the circuit operates in a normal operation mode, the data receive port receives data transmitted from the data send port via the data line, in response to the self-generated receive clock. Accordingly, the amount of interconnection delay of the data line is previously captured and data is received in response to the self-generated receive clock. Thus, the operation timing margin of the data receive port is increased. Also, a separate clock line is not required, and the send clock is supplied to the data receive port via the data line only upon abnormal operation of the semiconductor integrated circuit, so that power consumption is reduced.

28 citations

Patent
21 Nov 1984
TL;DR: In this article, a dummy bit line (60) is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase (PHI2).
Abstract: Glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line (60) is added to the memory arrangement which is always precharged during a first clock phase (PHI1) and discharged during a second clock phase (PHI2). The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

28 citations

Patent
Toshiyuki Matsubara1
16 Feb 1993
TL;DR: In this paper, a non-contact integrated card includes a data transmitting and receiving circuit, a data processing unit connected with the data transmission and receiving circuits, a clock generating circuit for generating a clock signal and for supplying the clock signal to the data processing units, a battery for supplying electrical energy to the transmission and reception circuits, the clock processing unit and the clock generator, and a clock stopping circuit for stopping the generation of the signal by the generator upon receiving a clock stop signal from outside the card.
Abstract: A non-contact integrated card includes a data transmitting and receiving circuit, a data processing unit connected with the data transmitting and receiving circuit, a clock generating circuit for generating a clock signal and for supplying the clock signal to the data processing unit, a battery for supplying electrical energy to the data transmitting and receiving circuit, the data processing unit and the clock generating circuit, and a clock stopping circuit for stopping the generation of the clock signal by the clock generating circuit upon receipt of a clock stop signal from outside of the card. The inclusion of the clock stopping circuit which stops the generation of the clock signal in response to a clock stop signal input from an external circuit makes it possible to suspend the consumption of energy produced by the battery after testing, during shipping, and before use of the card.

28 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884