Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Clock synchronization circuit and clock synchronizing method in baseband demodulator of digital modulation type

Abstract: A clock synchronization circuit for use in a baseband demodulator of communication equipment of a digital modulation type, in which detection data is subjected to an interpolating operation with respect to at least one point between adjacent two sample values of the detection data, subjected to a conversion into one-bit data indicative of a positive or negative value, and then passed through a one-bit-input band pass filter to perform phase error detection. Consequently, clock synchronization accuracy is improved while preventing a sampling rate and circuit scale from being made large.

A concurrent model for de-synchronization

Abstract: This paper shows how asynchronous circuits can be derived from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A concurrent model for de-synchronization is presented and behavioral properties are proved. A case study shows the applicability of the method and the potential benefits of de-synchronizing synchronous circuits.

Multiple interval single phase clock

Abstract: A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired. Error detection circuitry is provided to ensure proper operation of the circuitry generating the enable signals.

System and method for correcting timing signals in integrated circuits

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Clock generator circuit stabilized over temperature, process and power supply variations

Abstract: A clock generator circuit incorporates a sub-PTAT (proportional to absolute temperature) current source and a super-PTAT current source for generating bias currents for a voltage reference generator and charging currents for a voltage ramp generator. The clock generator circuit further includes a linear comparator coupled to receive one or more switching voltage reference signals and a voltage ramp signal and generate a switching output signal as the clock signal. The clock signal is coupled to a clock decoder to generate the desired clock signals having the desired phase. The functional blocks of the clock generator circuit of the present invention operate together to generate a highly frequency stable clock signal. In one embodiment, the linear comparator incorporates a dual-differential-input (dual-channel) instrumentation amplifier as the comparator input stage to generate clock signals having clock frequency errors that are minimized over process, temperature and power supply variations.