Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Driving method of an electric circuit

Abstract: A variation in threshold may be suppressed by structuring an analog switch by a MOS transistor and forming a signal synchronized to a clock by making the clock which is a common signal in continuity or discontinuity. An object of the present invention is to reduce the variation in the signal synchronized to the clock by the variation in threshold of the MOS transistor in a circuit which is synchronized to the clock.

Method, apparatus, and system to reduce microprocessor power dissipation

Abstract: A method and apparatus for reducing a microprocessor's power dissipation. In one embodiment a microprocessor includes a clock circuit, a core coupled to said clock circuit, and an on-die logic circuit coupled to said clock circuit to operate independent of a connection for power to said core, the on-die logic circuit includes a snoop request monitor coupled to a bus, and a snooping memory circuit.

On-die clock jitter detector for high speed microprocessors

Abstract: An on-die clock jitter detector has been designed for high speed microprocessor circuits and fabricated in 0.18 /spl mu/m CMOS technology. Variation of internal clock high/low time or period has been recorded. Innovative circuit techniques are used to provide fast initial DLL lock, adaptive filtering, granular jitter computation, and enhanced immunity to power-supply noise. It compares individual clock cycles to the average clock period, reporting the differences. The system has multiple output modes to allow more complete understanding of the jitter distribution and time dependence.

Fault-tolerant clock signal distribution arrangement

Abstract: A fault-tolerant clock signal distribution system for a plurality of equipment units is disclosed. Fault tolerance is achieved by independent bussing of clock signals from each of a pair of duplicated clock sources to a plurality of clock receiver units, each receiver unit associated with one of the plurality of equipment units and including sequential logic apparatus operative to examine the two clock signal trains bussed to the clock receiver unit and to ignore that signal train that phase lags the other. In case the phase leading clock source or its transmission bus fails, the remaining clock signal takes over. Because the outputs of the duplicated clock sources are distributed over separate busses, either source may comprise the phase-leading clock at any particular clock receiver unit. The phase difference between the two clock source outputs is kept small enough such that any resultant irregularity in the clock receiver unit output upon failure of one of the two clock sources or transmission busses will not affect the normal operation of the equipment units served by the clock distribution arrangement.

Resonant Clock And Interconnect Architecture For Digital Devices With Multiple Clock Networks

Abstract: A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).