Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks

Abstract: A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.

Data driven VLSI computation for low power DCT-based video coding

Abstract: The paper presents a VLSI architecture for the low-power and low-complexity implementation of 2D discrete cosine transform and its inverse (DCT/IDCT) in video coding applications. A circuit based on the Chen algorithm and the distributed arithmetic approach is described. Since DCT/IDCT coefficients are typically quite small we use a data driven clock gating strategy to turn off some portions of the circuit when operating on input data equal to zero or whose most significant bits are just sign extensions. For typical H.263/MPEG video coding applications this approach provides 26% and 36% power reduction in the DCT and IDCT modes, respectively.

Reducing energy consumption in wireless devices

Abstract: Techniques are provided for reducing power consumption in wireless communication devices During an idle listening period, the clock rate of the receiver in the device is reduced Data packets received by the receiver are then sampled at the reduced clock rate A determination is made as to whether the data packet is intended for the device The clock rate is restored to the full clock rate when the data packet is intended for the device On the other hand, the receiver continues to operate at the reduced clock rate when the data packet is not intended for the device

Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM

Abstract: In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row co-controlled capabilities. The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2/spl times/ to 20/spl times/ memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.

Fast timing-model independent buffered clock-tree synthesis

Abstract: In high-performance synchronous chip design, a buffered clock tree with small clock skew is essential for improving clocking speed. Due to the insufficient accuracy of timing models for modern chip design, embedding simulation into a clock-tree synthesis flow becomes inevitable. Consequently, the runtime for clock-tree synthesis becomes prohibitively huge as the complexity of chip designs grows rapidly. To construct a buffered clock tree efficiently, we propose an ultra fast timing-model independent approach to perform skew minimization by structure optimization. To achieve the goal, a novel clock-tree structure, called symmetrical structure, is presented. At each level of a symmetrical clock tree, the number of branches, the wire-length, and the inserted buffers are almost the same. It is natural that the clock skew could be minimized if the configurations of all paths from the clock source to sinks are similar. By symmetrically constructing a clock tree, the clock skew can be minimized without referring to simulation information. Experimental results show that our approach can not only efficiently construct a buffered clock tree, but also effectively minimize clock skew with marginal wiring overheads. Based on a set of commonly used IBM benchmarks, for example, a state-of-the-art work without (with) ngspice simulation results in averagely 7.93X (2.77X) clock skew and requires 46X (24343X) runtime over our approach.