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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
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Patent
Robert William Hulvey1
30 Jul 2003
TL;DR: In this paper, a dual mode clock for providing first and second clock signals to a wireless interface unit is proposed, where the transceiver in the RF analog module is turned off and the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface.
Abstract: A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second operating states of the wireless interface unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having low phase-noise characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface. By switching between low-power mode and normal mode, the system is operable to provide a high quality clock signal for use by the RF analog module when it is operational and to provide a lower power, lower quality clock signal which is sufficient for use by the baseband digital unit when the transceiver in the RF analog module is powered down.

28 citations

Patent
21 Jun 2002
TL;DR: In this paper, a phase controller adjusts the phase of the clock based on the filtered early and late indications of the data and the clock, with an input to the phase controller to adjust the phase so as to continually correct the frequency difference.
Abstract: A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

28 citations

Patent
30 Oct 1995
TL;DR: In this paper, a programmable circuit for generating a clock signal is described, which combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip.
Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

27 citations

Patent
22 Mar 1993
TL;DR: In this paper, an apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus.
Abstract: An apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus. Latching means and gating means are coupled to CPU and the output ports to control the clock signal received. The input port receives a change frequency signal. In response, the CPU executes the instructions from the instructing means to store the contents of the CPU's internal registers into memory. The CPU then generates a frequency select signal and a reset signal that resets itself. The latch means stores and outputs the frequency select signal to the gating means. The gating means uses the frequency select signal to output one of a plurality of different frequency clock signals received at its select input as the operating clock input of the CPU. The CPU thereafter operates under the newly gated clock signal. After the CPU reset is complete, the CPU reloads its internal registers with the information stored within the memory.

27 citations

Patent
21 Mar 2001
TL;DR: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a high-density memory array core coupled to the processing units.
Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884