Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Reducing clock skew variability via cross links

Abstract: Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wire-length. In this paper, we suggest to construct a low cost non-tree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2 increase of wirelength.

Programmable clock generator

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Integrated logic circuit with clock skew adjusters

Abstract: In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially equalized.

Synchronous dynamic random access memory

Abstract: A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.

Gated clock routing for low-power microprocessor design

Abstract: This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a clock-tree topology based on the locations and the activation frequencies of the modules, while the locations of the internal nodes of the clock tree (and, hence, the masking gates) are determined using a dynamic programming approach followed by a gate reduction heuristic. This work assumes that the gates are turned on/off by a centralized controller. Therefore, the additional power and routing area incurred by the controller and the gate control signal routing are examined. Various tradeoffs between power and area for different design options and module activities are discussed and detailed experimental results are presented. Finally, good design practices for implementing the gated clocks are suggested.