Topic
Clock gating
About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.
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Patent•
19 Mar 1999
TL;DR: In this paper, a charge pump for providing a desired boosted output voltage, a plurality of boosting stages are connected in series, and the pump also has a clock signal supply circuit for providing clock signals and a boost circuit for boosting the clock signals.
Abstract: In a charge pump for providing a desired boosted output voltage, a plurality of boosting stages are connected in series. The pump also has a clock signal supply circuit for providing clock signals and a boost circuit for boosting the clock signals. Clock signals derived from the clock signal supply circuit are supplied to each of the boosting stages on a former side. In contrast, a boosted clock signal derived from the clock signal boost circuit and a clock signal derived from the clock signal supply circuit are supplied to each of the boosting stages on a latter side.
91 citations
Patent•
28 Apr 1999TL;DR: In this article, a synchronizing circuit accomplishes phase synchronization between a signal from a node nearest to the clock distributing circuit with an external clock signal through a plurality of clock transmission nodes arranged in a tree.
Abstract: To input buffers included in a peripheral pad group inputting an external signal and a DQ pad group for data input/output, clock signals from a synchronizing circuit are transmitted through a clock distributing circuit having a plurality of clock transmission nodes arranged in a shape of a tree. The synchronizing circuit accomplishes phase synchronization between a signal from a node nearest to the clock distributing circuit with an external clock signal. Thus, a skew in clock signals applied to the input and output buffers can be eliminated.
91 citations
03 Jan 2005
TL;DR: In this article, a new approach to global clock distribution is presented, in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance, with reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network.
Abstract: This work presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-/spl mu/m CMOS technology.
91 citations
Patent•
03 Sep 1993TL;DR: A time measurement system for measuring time accurately with an inaccurate clock, in which two clock oscillators are compared and the momentary error of the slower clock oscillator is measured, is described in this article.
Abstract: A time measurement system for measuring time accurately with an inaccurate clock, in which two clock oscillators are compared and the momentary error of the slower clock oscillator is measured. When the error change rate of the slower clock oscillator is slow enough the fast clock oscillator can be switched off for longer time intervals. With the help of this apparatus and method of operation power can be saved in portable equipment which requires accurate time measurement.
89 citations
TL;DR: Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively.
Abstract: First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.
89 citations