Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

TACO: temperature aware clock-tree optimization

Abstract: In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO, while tries to minimize the worst case clock skew, also attempts to minimize the clock tree wirelength by building up merging diamonds in a bottom-up manner. As an output, TACO provides balanced merging points and the modified clock routing paths to minimize the worst case clock skew under thermal variation. Experimental results on a set of standard benchmarks show 50-70% skew reduction with less than 0.6% wirelength overhead.

A method and apparatus for generating and distributing clock signals with minimal skew

Abstract: A memory controller and at least one memory module exchange data at high transfer rates by minimizing clock skew. When writing data to the memory module, the memory controller generates a clock signal that travels along a first clock line segment. The data bus carries the write data, and the electrical characteristics of the data bus and first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory module in fixed relation to one another. When reading data, the first clock line segment is looped back from the memory module to the memory controller along a second clock line segment, with a copy of the clock signal provided on the second clock line segment. The data bus carries the read data, and the electrical characteristics of the data bus and the first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory controller in fixed relationship to one another. The present invention provides a substantial increase in memory bandwidth with minimal design changes to prior art memory systems.

Identifying program power phase behavior using power vectors

Abstract: Characterizing program behavior is important for both hardware and software research. Most modern applications exhibit distinctly different behavior throughout their runtimes, which constitute several phases of execution that share a greater amount of resemblance within themselves compared to other regions of execution. These execution phases can occur at very large scales, necessitating prohibitively long simulation times for characterization. Due to the implementation of extensive clock gating and additional power and thermal management techniques in modern processors, these program phases are also reflected in program power behavior, which can be used as an alternative means of program behavior characterization for power-oriented research. In this paper, we present our methodology for identifying phases in program power behavior and determining execution points that correspond to these phases, as well as defining a small set of power signatures representative of overall program power behavior. We define a power similarity metric as an intersection of both magnitude based and ratio-wise similarities in the power dissipation of processor components. We then develop a thresholding algorithm in order to partition the power behavior into similarity groups. We illustrate our methodology with the gzip benchmark for its whole runtime and characterize gzip power behavior with both the selected execution points and defined signature vectors.

Low skew clock tree circuit using variable threshold voltage transistor

Abstract: PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew

Low-power system clock calibration based on a high-accuracy reference clock

Abstract: Various techniques are described for periodically performing a calibration routine to calibrate a low-power system clock within an implantable medical device (IMD) based on a high accuracy reference clock also included in the IMD. The system clock is powered continuously, and the reference clock is only powered on during the calibration routine. The techniques include determining a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles, and adjusting a trim value of the system clock to compensate for the clock error. Calibrating the system clock with a delta-sigma loop, for example, reduces the clock error over time. This allows accurate adjustment of the system clock to compensate for errors due to trim resolution, circuit noise and temperature.