Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition

Abstract: A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 231 -1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.

Reducing computer power consumption by dynamic voltage and frequency variation

Abstract: A method for dynamically varying the power consumption of computer circuits (20) under program control. A power control subsystem (22) determines the minimum required level of power (52;Fig. 2) based on a number of factors (Fig. 3) including the particular operation and the recent amount of idle time of the circuit. Voltage (42) and clock speed (38) are determined for the circuit (20) to provide the minimum level of power. The system (22) for controlling the power consumption of the computer circuit (20) comprises a power control subsystem (22) for determining the power level (24), a sequencer (26) for controlling the change in voltage and clock speed, a variable voltage source (40), and a variable clock source (36).

System and method for managing power consumption within an integrated circuit

Abstract: An integrated circuit includes power gating circuits for coupling an associated circuit block with a power supply voltage. The power gating circuits also generate power consumption measurements for the associated circuit blocks. A power manager for the integrated circuit may manage the overall power consumption of the integrated circuit and may individually turn on and off the circuit blocks using the power gating circuits.

Embedded clock recovery and difference filtering for an MPEG-2 compliant transport stream

Abstract: A method of decoding a bitstream having an embedded clock, where the clock reference data is recovered from the bit stream. The clock reference data is combined, typically subtracted, from the system time clock to generate a result. This result is input to a pulse width modulator to form a pulse train, which is used to generate an input to a timing device.

Synchronous/asynchronous clock net with autosense

Abstract: A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is operating in a synchronous or asynchronous fashion, while the circuit still minimizes clock skew between the internal bus clocks of both clock domains as well as any corresponding external bus clocks.