Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Method and apparatus for supporting power conservation operation modes

Abstract: An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock (430) that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit (420) is coupled to the clock enable circuit (430). The time-wise independent time reference circuit (420) sends the first signal to the clock enable circuit (430) a first predetermined period of time after receiving a signal to enter into a suspend state.

CPU clock control unit

Abstract: The present invention relates to an apparatus and method for controlling a CPU clock in response to certain events with a system in order to conserve power usage. These events can be programmably enabled or disabled. The apparatus comprises a circuit for detecting enabled Stop Clock events requiring the CPU clock to temporarily cease operation. In combination therewith, the present invention includes a circuit for detecting enabled Stop Break events which are used to re-start the CPU clock. The present invention further comprises a Speedup circuitry to increase the CPU clock speed for enabled speedup events which are dependent on CPU clock speed.

Self calibrating clocks for globally asynchronous locally synchronous systems

Abstract: We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local clock domain is made possible by stretching the local clock if a metastable condition could be encountered. Stretching the clock just requires the rising clock edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.

Clock-gating circuit for reducing power consumption

Abstract: A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Common-mode output sensing circuit

Abstract: A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P 1 ) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V AGO ) during a second clock phase, which increases the output loading during the second clock phase (P 2 ). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P 1 ) to match the load produced by the refresh circuit (604) during the second clock phase (P 2 ).