Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Resonant tree driven clock distribution grid

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Clock multiplication circuit and method

Abstract: An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Environment-aware clock skew estimation and synchronization for wireless sensor networks

Abstract: Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate clock skew, the inherent reason causing clock desynchronization, is investigated. According to the measurement results, clock skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist clock skew estimation. Using AMKF, an environment-aware clock synchronization (EACS) scheme is proposed to dynamically compensate clock skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the clock is updated with local information before the clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of clock skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

Core clock correction in a 2/N mode clocking scheme

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Energy-Efficient Register Access

Abstract: We present and evaluate seven techniques to reduce energy dissipation for accesses to a processor register file: modified storage cell avoids bitline discharge for zero bits, precise read control avoids fetching unused operands, latch clock gating disables latch clocks when operands are not needed, bypass skip turns off regfile reads when bypass circuitry will supply the value, bypass RO treats accesses to RO separately, split bitline reduces access energy for frequently-used registers, and read caching avoids regfile reads when the same register is read twice in succession. For a 0.25 /spl mu/m CMOS three-port regfile, we find individual energy savings of 27%, 21%, 8%, 16%, 14%, 12%, and 1% respectively and a combined saving of 59% when all seven techniques are used in combination. The total area overhead is around 17% and the total delay overhead is around 3%.