Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Data processor and single-chip microcomputer with changing clock frequency and operating voltage

Abstract: A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of circuit modules can be dynamically changed according to the content of a packaged register. If the content of the register instructs the reduction of the clock signal frequency and the operating voltage in its absolute value, the operating voltage is lowered in its absolute value prior to the change in the clock signal frequency. On the contrary, if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signal having the increased frequency is outputted prior to the increase of the operating voltage in the absolute value. As a result, it is possible to prevent in advance the malfunctions of the circuit at the time of switching the operation frequency and the operating voltage of the circuit module.

Understanding and minimizing ground bounce during mode transition of power gating structures

Abstract: We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques.

A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants

Abstract: This paper presents an integrated neural stimulator with highly efficient and flexible frontend which is intended for an epiretinal implant with 1024 electrodes. It features programmable stimulation pulse shapes, a high-voltage (HV) output driver with compliance monitor for supply voltage adaptation, active and passive charge balancers, and electrode impedance measurement. Area and power efficiency is achieved by global timing assignment and local amplitude control over a bus at the local stimulation units. Major power savings in the distributed digital control units are realized by implementing global and local clock gating. Two stimulator frontends have been fabricated in a 0.35 μm HVCMOS process. Each frontend features four demultiplexed outputs and consumes 0.2 mm2 core area. A maximum voltage compliance of 20 V is achieved and up to 1 mA of output current can be adjusted with up to 50 dB dynamic range. In vitro experimental results performed on a platinum black electrode in 0.9% saline solution are given.

A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor

Abstract: Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies /spl ges/2 GHz for the core and /spl ges/4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle.

Method and apparatus for on-demand power management

Abstract: An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.