Topic
Clock gating
About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.
Papers published on a yearly basis
Papers
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18 Oct 2001
TL;DR: In this paper, a duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal with an arbitrary duty cycle is presented. But the method is not suitable for the case of a single-input single-output (SISO) clock.
Abstract: A duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal having an arbitrary duty cycle. Once the input clock signal is received, an output clock storage element is switched to a first state upon detecting a transition in the input clock signal for driving the output clock signal to a first signal level. The output clock storage element is then switched to a second state after a delay interval equal to a fraction of the period for driving the output clock signal to a second signal level. The fraction of the period can be programmed to a pre-selected value.
60 citations
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IBM1
TL;DR: In this paper, a method for estimating the total heat accumulated for dissipation at any given time is described and the clock rate is decreased to reduce heat generation for the periods that the chip is idle.
Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.
59 citations
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28 Feb 1997TL;DR: In this paper, a clock domain translation circuit for communicating a digital signal from a high speed clock domain to a low-speed clock domain is disclosed. But, the clock signal is held for enough time to be properly clocked in, depending upon the phase region, thus enabling frequency ratios of noninteger values to be utilized in system operation.
Abstract: A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at different multiples of a system clock signal. The clock generation circuitry (20) includes a counter (60) that indicates, for a given frequency ratio, signals (REGION) indicating the current phase region of the faster clock (PCLK) relative to the slower clock (BCLK). The clock domain translation circuit (50a) includes a series of input registers (82, 84) in sequence, with the output of each as well as the input signal line (IN PCLK) coupled to inputs of a multiplexer (80). The multiplexer (80) selects either the input signal directly or the output of one of the registers for application to an output register (90), clocked by the slower clock signal (BCLK), depending upon the phase region of the faster clock (PCLK) relative to the slower clock (BCLK) for communication of that signal. As a result, the input digital signal is held for enough time to be properly clocked in, depending upon the phase region, thus enabling frequency ratios of non-integer values to be utilized in system operation.
59 citations
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18 Sep 2006TL;DR: Hierarchical power distribution with a power tree has been developed and leakage currents of a 1,000,000-gate power domain were effectively reduced to 1/4,000 in multi-CPU SoCs with minimal area overhead.
Abstract: Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor
59 citations
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TL;DR: Simulated results of a fully integrated 650 Mbit/s clock recovery circuit designed in an existing 0.9 μm CMOS technology are presented.
Abstract: Clock recovery circuits based on matched gated oscillators are proposed. Lock is acquired on the first data transition, even with non-return-to-zero line coding and with instantaneous and arbitrarily large phase shifts of the incoming signal. Simulated results of a fully integrated 650 Mbit/s clock recovery circuit designed in an existing 0.9 μm CMOS technology are also presented.
59 citations