Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Automatic signal delay adjustment apparatus

Abstract: Apparatus for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, automatic de-skewing circuitry is provided on each of a plurality of clock distribution chips for de-skewing the clock outputs from different chips. In a preferred implementation of the de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Zero-delay buffer circuit for a spread spectrum clock system and method therefor

Abstract: A clock recovery circuit and a method for reduced electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generate an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Low power, testable dual edge triggered flip-flops

Abstract: Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (up to 50%). Two main approaches have been suggested to reduce clock dissipation: clock gating and low power flip-flops. In this article we address the latter. We demonstrate that the usage of double edge triggered flip-flops results in a power reduction of 50% in the clock net, and in a reduction of up to 45% inside the flip-flops. Furthermore, we consider other flip-flop parameters, like setup and hold times, propagation delay and testability.

Resonant-Clock Latch-Based Design

Abstract: This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their clock distribution networks. It also highlights RCL, a novel resonant-clock latch-based methodology that was used to design the two test-chips. RF1 and RF2 are 8-bit 14-tap finite-impulse response (FIR) filters with identical architectures. Designed using a fully automated ASIC design flow, they have been fabricated in a commercial 0.13 mum bulk silicon process. RF1 operates at clock frequencies in the 0.8-1.2 GHz range and uses a single-phase clocking scheme with a driven clock generator. Resonating its 42 pF clock load at 1.03 GHz with Vdd = 1.13 V, RF1 dissipates 132 mW, achieving a clock power reduction of 76% over conventional switching. RF2 achieves higher clock power efficiency than RF1 by relying on a two-phase clocking scheme with a distributed self-resonant clock generator. Resonating 38 pF of clock load per phase at 1.01 GHz with Vdd = 1.08 V, RF2 dissipates 124 mW and achieves 84% reduction in clock power over conventional switching. At 133 nW/MHz/Tap/InBit/CoeffBit, RF2 features the lowest figure of merit for FIR filters published to date.

Clock distributing circuit

Abstract: A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.