Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Clock control system for microprocessors including a delay sensing circuit

Abstract: A microprocessor includes a clock control system for varying its internal processor clock frequency. The clock control system includes a delay chain composed of delay elements. A set of tap points are distributed at the outputs of selected delay elements. Each tap point is coupled to a respective input line of a latch unit. During operation, an external clock generator provides a clock signal to an input of the delay chain. As a particular rising or falling edge of the clock signal propagates through the delay chain, corresponding signal transitions sequentially appear at the tap points. The latch unit stores the signals in response to a subsequent rising or falling edge of the external clock signal. Thus, an output of the latch unit is indicative of a delay associated with the microprocessor. A decoding circuit may be provided to decode the output of the latch unit and to provide an input to a clock switching circuit which controls the frequency of an internal clock signal. If a high propagation delay exists, the frequency of the internal clock is decreased. If a low propagation delay exists, the frequency is increased.

Stretching the limits of clock-gating efficiency in server-class processors

Abstract: Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4/spl trade/ or POWER5/spl trade/ class). We then look beyond classical clock-gating: we examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular, we examine the power reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating. Based on our experiences with current designs, we try to bound the practical limits of clock gating efficiency in future microprocessors.

Clock driver with instantaneously selectable phase and method for use in data communication systems

Abstract: A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal having a periodic wave form and provides the flexibility for selecting or changing the magnitude of the phase-offset of the output clock signal, in relationship to the input clock signal, for desired clock periods and optionally desired half-clock periods. A method is provided for the self-calibration of critical delay elements. The present invention also includes a method for synchronizing data transfers between a bus master device that is clocked by a system clock and a plurality of synchronous DRAM devices (SDRAM) that are clocked by a local clock; the local clock has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. A Dual In Line Module (DIMM) of the present invention receives a system clock signal and provides a local clock signal to an array of SDRAM devices, wherein the local clock signal has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. Optionally the magnitude of the phase-offset of the local clock signal is selectable through software providing the flexibility to support a method for determining the optional phase-offsets by software using an iterative process involving trial and error.

Automatic clock tuning and measuring system for LSI computers

Abstract: An automatic clock tuning and measuring system is provided for data processing system wherein fixed frequency clock pulses are selectively delayed and distributed in accordance with a clock path and delay selection made by a computing means. A reference generator is connected to the fixed frequency clock pulses source for delaying the clock pulses a reference amount which is selected by the computing means in accordance with the predetermined delay associated with the selected path. An automatic time measuring means is connected to both the reference generator and the clock distribution means for providing an output indicative of the time comparison condition of a delayed clock pulse and the reference delayed clock pulse. The output time comparison or non-comparison of the delayed clock pulse and the reference delayed clock pulse is utilized through the computer means to adjust the amount of delay introduced by the automatic delay means or is utilized to adjust the delay increment established in the reference generator to provide the clock tuning and measuring respectively.

Obtaining and exporting on-chip data processor trace and timing information

Abstract: An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.