Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Normalization of apparent propagation delay.

Abstract: An integrated circuit includes a clock alignment circuit (10) having a frequency synthesizer (12) for receiving a reference clock signal (CLKIN) at a lower frequency and for generating phases (CLK1, CLK2, CLK3, CLK4) of an oscillator clock signal at a higher frequency. The oscillator clock signal phases (CLK1, CLK2, CLK3, CLK4) drive a desired clock signal phase generating circuit 26 that generates various phases of the desired clock signal. The desired clock signal phases (CLK1, CLK2, CLK3, CLK4) are systematically compared to the reference clock signal (CLKIN). The phase of the desired clock signal that is determined to align with the reference clock signal (CLKIN) is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator (20) in the frequency synthesizer (12) to align the selected phase of the desired clock signal with the reference clock signal (CLKIN).

Method and apparatus for reducing standby current in communications equipment

Abstract: A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

An envelope-following method for the efficient transient simulation of switching power and filter circuits

Abstract: The transient behavior of circuits like switching power converters and switched capacitor filters are expensive to simulate because they are clocked at a frequency whose period is orders of magnitude smaller than the time interval of interest to the designer. It is possible to reduce the simulation time without compromising accuracy by exploiting the fact that the behavior of such a circuit in a given high-frequency clock cycle is similar, but not identical, to its behavior in the preceding and following cycles. In particular, the envelope of the high-frequency clock can be followed by accurately computing the circuit behavior over occasional cycles. The authors describe the implementation of an envelope-following method that is particularly efficient for switching power and filter circuits, and they present results demonstrating the method's effectiveness. >

Adjusting voltage supplied to a processor in response to clock frequency

Abstract: A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit is provided. A request signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. A frequency detection circuit monitors the clock signal and causes a voltage regulator to reduce the voltage supplied to the integrated circuit in response to the reduced clock frequency. Similarly, a request signal is sent to the clock, and in response, the clock raises the clock frequency supplied to the integrated circuit. The frequency detection circuit monitors the clock signal and causes a voltage regulator to raise the voltage supplied to the integrated circuit in response to the increased clock frequency. The slew rate of the clock is controlled so that at least a minimum required voltage for each operating frequency is provided while the clock frequency is being changed. In this manner, reliable operation of the processor is assured while the clock speed and operating voltage are being changed.

Semiconductor device using complementary clock and signal input state detection circuit used for the same

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.