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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Proceedings ArticleDOI
18 Jun 2007
TL;DR: A 90nm buck converter is intended for complex multi-core ICs and using the 3GHz system clock for switching reduces the area to 0.27mm2 and allows the output filter to be integrated.
Abstract: A 90nm buck converter is intended for complex multi-core ICs. Using the 3GHz system clock for switching reduces the area to 0.27mm2 and allows the output filter to be integrated. Efficiency is increased by recycling clock charge and delivering it to the load instead of ground. A dedicated 3GHz clock circuit driving 12pF consumes 39.9mW. In contrast, a combined clock and converter circuit consumes 56.2mW and delivers 25.7mW at the converter output. Regulation is achieved through PWM of the clock. The circuit converts 1.0V to between 0.5 to 0.7V at 40 to 100mA.

53 citations

Proceedings ArticleDOI
30 Aug 2006
TL;DR: Compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.
Abstract: Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA’s large static power consumption.

53 citations

Patent
24 Oct 2000
TL;DR: In this article, a computer system that is able to switch processor and bus frequencies, along with processor voltage, when the system is placed into AC from battery power mode, and when the systems are placed into battery from AC power mode.
Abstract: A computer system that is able to switch processor and bus frequencies, along with processor voltage, when the system is placed into AC from battery power mode, and when the system is placed into battery from AC power mode. The computer system includes transitioning a processor (CPU) into a low performance mode using a clock generator that provides different clock frequencies, a high performance clock frequency and a low performance clock frequency depending on whether battery or AC power is used. The processor and interconnecting busses use the lower clock frequency in order to save battery power.

53 citations

Patent
Takashi Tsunoda1
17 Jun 1977
TL;DR: In this article, a control circuit was proposed to reduce the number of clock pulses required for keeping an electronic component in a waiting condition or state, thereby minimizing the heat dissipation thereof.
Abstract: A minimum number of clock pulses required for keeping an electronic component in a waiting condition or state are intermittently applied to the electronic component, thereby minimizing the heat dissipation thereof. A control circuit, utilized in the invention, provides an output signal which permits continuous clock signals to be applied, for example, to memory chips, during read and write periods, but such control circuit reduces the number of clock signals applied to the memory chips during periods when the read and write processes are not required.

53 citations

Proceedings ArticleDOI
01 Dec 2010
TL;DR: This paper proposes a modification to the fabric of an FPGA that enables dynamically-controlled power gating, in which logic clusters can be selectively powered-down at run-time, for applications containing blocks with large idle times, which could lead to significant leakage power savings.
Abstract: Leakage power is an important component of the total power consumption in FPGAs built using 90nm and smaller technology nodes. Power gating, in which regions of the chip can be powered down, has been shown to be effective at reducing leakage power. However, previous techniques focus on statically-controlled power gating. In this paper, we propose a modification to the fabric of an FPGA that enables dynamically-controlled power gating, in which logic clusters can be selectively powered-down at run-time. For applications containing blocks with large idle times, this could lead to significant leakage power savings. Our architecture utilizes the existing routing fabric and unused input pins of logic clusters to route the power control signals. No modifications to the existing routing algorithms are required to support the new architecture. We study the area and power tradeoffs by varying the basic architecture parameters of an FPGA, and by varying the size of the power gating regions. We also study the leakage energy savings using a model that characterizes an application in terms of its structure and behavior. We show less than 1% of area overhead for a power gating region size of 3X3 logic tiles. Using the application model, we show that up to 40% leakage energy reduction can be achieved using the proposed architecture for different application parameters, not including power dissipated by the power state controller.

53 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884