Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Glitch free clock select switch

Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.

Clock supplying circuit and integrated circuit device using it

Abstract: A clock supplying circuit that supplies a clock to a plurality of controlled circuits 451-454 arranged in respectively different positions. A forward and backward wiring 41, 42 and an internal clock supply wiring 43 are arranged along controlled circuits. A main clock drive circuit 40 is for outputting a first clock to the forward wiring 41 and is for outputting a second shorter phase than the first clock to the internal clock supply wiring 43. A plurality of local clock drive circuits 441-444 arranged close to the controlled circuits, are supplied with a forward clock propagated along the forward wiring and with a back clock propagated along the backward wiring, and are also supplied with the second clock, for delaying the phase of the supplied second clock so as to coincide with a phase intermediate the forward clock and the back clock, and for supplying the delayed clock of the second clock to the respectively corresponding controlled circuits as local clock.

Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device

Abstract: A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

Abstract: This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called “template matching” for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85°C.

Digital phase-locked loop circuit with reduced phase jitter frequency

Abstract: A digital phase-locked loop (DPLL) ( 22 ) for use in one or more integrated circuits ( 20 ) that may be combined within an electronic system is disclosed. The DPLL ( 22 ) includes a phase detector ( 30 ) that generates a shift clock and a shift direction signal responsive to a phase difference between a system clock and a feedback clock. The shift direction signal is stored in a latch ( 32 ), applied to one input of an exclusive-NOR gate ( 34 ), and to shift direction inputs (R/{overscore (L)}) of first and second digital delay lines ( 38, 42 ). The first digital delay line ( 38 ) receives the system clock and generates a delayed clock that is distributed within the integrated circuit ( 20 ) by clock distribution circuitry, and that is applied to an input of the second digital delay line ( 42 ); the second digital delay line ( 42 ) generates the feedback clock that is received by the phase detector ( 30 ). The shift clock is gated from application to the first and second digital delay lines according to the comparison of the current shift direction with that stored in the latch ( 32 ), such that the shift clock is applied to the shift clock input of the first digital delay line ( 38 ) to adjust its delay only upon the phase detector ( 30 ) detecting a phase differential of the same polarity at least twice in a row; the shift clock is applied to the shift clock input of the second digital delay line ( 42 ) upon the phase detector ( 30 ) detecting opposite phase differentials in the current and previous phase detection events.