Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

A novel clock distribution and dynamic de-skewing methodology

Abstract: In present day VLSI ICs, intra-die processing variations are becoming harder to control, resulting in a large skew in the clock signals at the end of the clock distribution network We describe a buffered H-tree technique to distribute the clock signal and to de-skew a clock network The clock shielding wires (which are connected to GND in normal operation) are, in de-skewing mode, used to selectively return the clock signal for de-skewing, and for serial communication with the clock distribution sites for skew adjustment Our forward and return clock networks are buffered, with identically sized and co-located wires and buffers This results in both these networks exhibiting identical delay characteristics in the presence of intra-die process variations Unlike existing approaches, our method utilizes a single phase detection circuit, and can achieve a very low maximum chip-level clock skew This skew value is not dependent on the resolution of the phase detector Further, our technique can be applied dynamically, either at boot time or periodically during the operation of the IC, as necessary Additionally, our buffered H-tree enables us to implement efficient clock gating by allowing the user to turn off clocks in the distribution network itself, thus disabling entire sections of the clock network We demonstrate the utility of our technique on a 6-level H-tree clock distribution network In a clock distribution network which is initially skewed by up to 300ps, our technique can de-skew signals to within 4ps of each other We show that the total wiring area of our clock distribution and de-skewing methodology is about 35% higher than a traditional H-tree (which does not have a deskewing functionality), while the active logic area overhead is about 25% The power consumption of our network is 5% lower than that of a traditional H-tree network with no de-skewing functionality

Challenges in clockgating for a low power ASIC methodology

Abstract: Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activity in the logic modules as well as by eliminating power dissipation in the clock distribution network. There is an inherent pitfall though in implementing gating groups for hierarchical gated clock distribution because the groups are typically developed at the logic level with no information of the physical layout of the clocktree. Depending on the distribution of underlying sinks, maintaining gating groups can cause a wiring overhead that is potentially greater than the savings due to reduced switching. We look at modifications of zero-skew tree algorithms to consider both the physical and logical aspects of hierarchical gating. The algorithms are applied to data taken from a low power ASIC design. The best gated clocktree is created using both physical and logical information.

Method and apparatus for providing clock signals to macrocells of logic devices

Abstract: A complex programmable logic device (CPLD) is disclosed which includes a set of logic blocks each containing a product term array and a set of macrocells. A clocking arrangement is provided which allows selection between synchronous and asynchronous clock signals for input to each macrocell. The clocking arrangement is hierarchical. More specifically, a synchronous clock multiplexer is provided, within each logic block, for reducing an input set of N synchronous clock signals, and their complements, to a reduced set of M synchronous clock signals. The selected synchronous clock signals, and J product term asynchronous clock signals, or their complements, provided by the corresponding product term array, are routed into each of the macrocells of the logic block. An additional multiplexer is provided within each macrocell for selecting one clock signal from among the M synchronous clock signals and the J product term signals. The hierarchical clocking arrangement provides considerable flexibility for selecting clocking signals, both on a block by block basis, and on a macrocell by macrocell basis yet requires relatively modest chip resources for implementation. A specific example is described herein where in N is six, M is three and J is one.

10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports

Abstract: A clock recovery architecture for recovering clock and serial data from an incoming data stream of a local area network station. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. A single clock generation module (CGM) and N phase multiplexers, one for each clock recovery channel on a chip, is used to select one of M phases of a 250 Mhz clock signal from the CGM for each clock recovery channel. To provide the required phase resolution, a phase interpolator is used. The phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer. Each phase multiplexer is advanced or retarded in response to the pump-up (pumpup) or pump-down (pumpdn) signals from each clock recovery channel (CRM).

SRTS clock recovery system implementing adaptive clock recovery techniques

Abstract: An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions. Once such an error is no longer anticipated, control is returned to the SRTS clock recovery system. Advantageously, data FIFO overflow and underflow conditions are prevented, thereby enabling the clock recovery system to provide error-free transmission through the implementing network node. The novel SRTS clock recovery system may make either temporary phase and/or permanent frequency adjustments to the transmit clock to recover from reference clock deviations without loss of data, without causing substantial perturbations in the transmit line frequency, while maintaining interoperability with existing SRTS equipment.