Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

System for distributing clocks using a delay lock loop in a programmable logic circuit

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Reducing power dissipation during test using scan chain disable

Abstract: A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the circuit. Moreover, disabling the clock also reduces power dissipation in the clock tree which often is a major source of power. The only hardware modification that is required to implement this approach is to add the capability for the tester to gate the clock for one subset of the scan chains in the core. A procedure for generating and ordering the test set to maximize the we of scan disable is described. Experimental results are shown indicating that the proposed approach can significantly reduce both logic and clock power during testing.

A 90-nm variable frequency clock system for a power-managed itanium architecture processor

Abstract: An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.

Disk drive employing vector addition of primary phase write clock signals for generating secondary phase write clock signal

Abstract: A disk drive includes a disk having a recording surface and a write element for writing a sequence of symbols in a continuous-time signal on the recording surface The disk drive includes a frequency generator for generating a plurality of primary phase write clock signals having a channel frequency f ch Each of the primary phase write clock signals has a selected primary phase shift from another one of the primary phase write clock signals The disk drive includes a programmable phase synthesizer for generating a secondary phase write clock signal having the channel frequency f ch and a selected secondary phase shift from one of the primary phase write clock signals The programmable phase synthesizer includes programmable means for selecting two of the primary phase write clock signals and element for performing vector addition of the selected primary phase write clock signals to generate the secondary phase write clock signal The secondary phase write clock signal is used for providing at least one of the symbols in the sequence of symbols to the write element

Delayed locked loop implementation in a synchronous dynamic random access memory

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.