scispace - formally typeset
Search or ask a question
Topic

Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
More filters
Proceedings ArticleDOI
05 May 1997
TL;DR: This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock gating techniques and shows that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.
Abstract: This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a derived clock for each flip-flop in the circuit. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.

47 citations

Patent
02 Apr 2001
TL;DR: In this article, a circuit that permits a processor in a microcontroller to adjust its clock speed on the fly is presented, where a processor receives a current clock signal and a phased current signal from a speed selection switch, and when the states of the current and new clocks appropriately align after a control from the processor, the new speed is switched into the current speed switch to permit the clock speed to change without producing spurious signals that cause unpredictable action in the processor.
Abstract: A circuit that permits a processor in a microcontroller to adjust its clock speed on the fly. A processor receives a current clock signal and a phased current clock signal from a speed selection switch. A new speed selection switch provides a new clock signal and a phased new clock signal for comparison with the current clock signals. When the states of the current and new clocks appropriately align after issuance of a control from the processor, the new speed is switched into the current speed switch to permit the clock speed to change without producing spurious signals that cause unpredictable action in the processor. This advantageously allows the microcontroller to adjust its clock speed under program control.

46 citations

Patent
Shin-Ichiro Akiyama1
13 May 1992
TL;DR: In this paper, a basic clock signal generating circuit for use in a single chip microcomputer includes a frequency divider receiving an external clock signal for generating a frequency-divided clock signal, and a waveform shaping circuit receiving the frequency-split clock signal output so as to generate a wave-form-shaped frequency-dispensing clock as a basic oscillation clock of a single-chip microcomputer.
Abstract: A basic clock signal generating circuit for use in a single chip microcomputer includes a frequency divider receiving an external clock signal for generating a frequency-divided clock signal, and a waveform shaping circuit receiving the frequency-divided clock signal output so as to generate a waveform-shaped frequency-divided clock as a basic clock of single chip microcomputer. An original oscillation clock generation circuit receives the external clock signal and generates an original oscillation clock having a frequency which is a-double of that of the basic clock. The basic clock and the original oscillation clock can be supplied to a peripheral circuit so that either the basic clock or the original oscillation clock can be selectively used in an internal circuit of the peripheral circuit.

46 citations

Proceedings ArticleDOI
10 Jan 1999
TL;DR: This paper presents a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control signal and presents an algorithm to estimate the power saving obtained by gating the clock and the performance penalty associated with the introduction of gating logic.
Abstract: In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock signal is a major source of dynamic power dissipation. Significant power savings can be obtained by identifying periods of inactivity in parts of the circuit, and disabling the clock to those parts of the circuit at the appropriate times. Selectively disabling the clock in this manner is referred to as clock gating. In this paper/sup 1/, we present a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control signal. We also generate the combinational logic to produce this control signal. We present an algorithm to estimate the power saving obtained by gating the clock and the performance penalty (if any) associated with the introduction of gating logic. The algorithm generates the clock gating logic which is inserted appropriately into the original circuit to produce a low power, gated clock version of the circuit.

46 citations

Patent
18 Feb 1997
TL;DR: In this paper, a real-time clock reset system is proposed to provide accurate time stamping of vehicle operational messages following a real time clock reset, which includes a processor, a memory and a clock powered by a constant power source.
Abstract: A system for providing accurately time stamped vehicle operational messages following a real-time clock reset includes a vehicle control computer having a processor, a memory and a real-time clock powered by a constant power source. The processor is operable to store a current value of the real-time clock in memory at engine shut down and to determine whether a clock reset event occurred since the previous engine operational cycle by testing a clock error flag in memory. If such a clock reset event occurred, the processor is operable to reset the real-time clock at the clock value stored at engine shut down and store this value in an error buffer of the memory. Upon establishment of communications with a time correction device having a master real-time clock, the processor is operable to determine whether the error buffer contains any clock values therein. If so, the processor is operable to correct the time stamps of all vehicle operational messages having time stamp values later than or equal to the clock value stored in the error buffer in accordance with the difference between the master clock value and the present value of the real-time clock, and to reset the real-time clock value to the master clock value.

46 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
89% related
Integrated circuit
82.7K papers, 1M citations
85% related
Electronic circuit
114.2K papers, 971.5K citations
85% related
Semiconductor memory
45.4K papers, 663.1K citations
83% related
Transistor
138K papers, 1.4M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884