Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Power-Aware Testing and Test Strategies for Low Power Devices

Abstract: Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This tutorial provides the fundamental and advanced knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during manufacturing test. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low-power design techniques and shows how low-power circuits and systems can be tested safely without affecting yield and reliability. Electronic Design Automation (EDA) solutions for testing low-power devices are also covered in the last part of the tutorial.

Internal clock signal generator including circuit for accurately synchronizing internal clock signal with external clock signal

Abstract: An internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) or phase locked loop (PLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.

The projected power consumption of a wireless clock distribution system and comparison to conventional distribution systems

Abstract: A wireless interconnect system has been proposed for global clock signal distribution. The system transmits and receives signals at 20 GHz or higher. The received signal is then amplified, frequency divided to 4 GHz or lower, and buffered to provide a clock signal to the local clock distribution system. An analysis comparing the projected power dissipation of a wireless clock distribution system to conventional grid-based and H-tree based distribution systems for 0.1 /spl mu/m generation microprocessors is performed, based on the total capacitive loading of the global distribution system. The results show that in terms of power dissipation, the wireless clock distribution system should be comparable to conventional systems.

Determination of Power Gating Granularity for FPGA Fabric

Abstract: In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is higher than that of coarse-grain power gating. Based on the placement and routing of benchmark designs in Spartan-3trade-like FPGA, guidelines for determining the granularity of power gating are provided. It is found that programmable resources with low utilization can be power gated more coarsely than the resources with high utilization