Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Method and apparatus for testing high performance circuits

Abstract: A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. Non-scannable memory elements are initialized via scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from a test clock or a system clock is generated to initialize the non-scannable elements.

Clock synchronous semiconductor memory device allowing testing by low speed tester

Abstract: Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

Evaluation on power reduction applying gated clock approaches

Abstract: In this paper the use of the gated clock approach to reduce power consumption is analyzed and compared. The approach has been implemented following three different strategies that allow the approach to be efficiently used under different design conditions. To verify the strength of the approach it has been implemented during the design of a programmable interrupt controller (PIC). The results found show a 2/spl times/ factor reduction in the average power consumption through the use of the three strategies. Moreover, the results have been also compared with those obtained through an automatic implementation of one of the gated clock strategies allowed by Synopsys's power compiler. In this second case only about 25% of power consumption is saved. It is worth noting that implementation of the three gated clock strategies leads also to a design with the smallest gate count.

Power management unit including software configurable state register and time-out counters for protecting against misbehaved software

Abstract: A power management unit including a set of time-out counters and a software configurable state register is provided for managing power consumption within a computer system. Depending upon the state of the power management unit, a power control unit and a clock control unit are configured such that power may be applied or removed from certain components of the computer system and such that the frequencies of a CPU clock signal and a system clock signal may be raised or lowered. The power management unit includes a software configurable state register which allows system software, such as APM responsive software within the system BIOS, to control the state of the power management unit. When the power management unit is in a ready state during which the CPU clock signal and the system clock signal are driven at maximum frequencies and during which power is applied to all computer components, a time-out counter is activated to begin a first count down period. A system monitor monitors various circuit portions of the computer system during this period, and, if certain system activity is not detected, the power management unit enters a doze state upon lapse of the time-out counter. During the doze state, the frequencies of the CPU clock signal and the system clock signal are reduced and/or power is removed from selected inactive circuit portions.

Zero latency synchronized method and apparatus for system having at least two clock domains

Abstract: A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay. The master and the slave of the input flip flop are controlled respectively by the first clock domain clock and by the first regenerated clock. In turn, the master and slave of the output flip flop are respectively controlled by the second regenerated clock and by the second clock domain clock. A signal to be transferred from the first clock domain to the second clock domain is input to the master of the input flip flop. The output from the slave of the input flip flop is provided as input to the master of the output flip flop.