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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


Papers
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Journal ArticleDOI
01 Jul 1997
TL;DR: A new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power and inspired by the Deferred-Merge Embedding approach, a merging segment perturbation procedure is devised to explore various tree configurations which result in correct clock operation under the required period.
Abstract: This paper presents a new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is useful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes together form the feasible solution space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explore various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible configurations, we adopt a simulated annealing approach to avoid being trapped in a local optimal configuration. This is complemented by a bi-partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of clock routing with zero-skew or a single fixed skew bound and separately sizing logic gates. This is achieved at no sacrifice of clock frequency.

44 citations

Patent
20 Oct 1998
TL;DR: In this article, a power-down circuit (72) in a lap-top computer cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit includes.
Abstract: A power-down circuit (72) in a lap-top computer (10) cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit (36) includes. In response to various stimuli, decoding logic (78) in the power-down circuit sends respective power-down-request signals to the various monitor circuits request permission to suppress application of respective clock signals to them. If a module's operational circuitry (82) is in a state in which clock removal is safe, the monitor circuit (80) responds with an acknowledgment signal, and the power-down circuit (72) causes a clock generator to interpret application of clock signals to the respective module (68). The monitor circuit (80) may additionally detect circumstances in which removing the clock signal from the operational circuitry (82) is safe only if the clock signal can subsequently be re-applied rapidly. In those circumstances, the monitor circuit (80) generates an idle signal that causes the power-down circuit (72) to stop clocking the associated operational circuitry but continue clocking the monitor circuit. In this way, the monitor circuit can keep operating so as to detect circumstances that will necessitate re-starting operational-circuit clocking. When it detects such a condition, it rapidly de-asserts the idle signal so that the clock signal is rapidly re-applied to the associated operational circuit.

44 citations

Patent
Sanghyeon Baeg1, Edward H. Yu1
18 Oct 1996
TL;DR: In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK as mentioned in this paper, which is then used to generate the normal operation of the circuit.
Abstract: In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.

44 citations

Patent
02 Feb 2001
TL;DR: In this article, a method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation is presented.
Abstract: A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.

44 citations

Proceedings ArticleDOI
13 Jun 2005
TL;DR: An opposite-phase scheme for peak current reduction is proposed, which can reduce the peak current of the clock tree nearly 50%.
Abstract: Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice.

44 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884