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Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.


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Patent
08 Nov 1996
TL;DR: In this paper, the operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio, and the maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN.
Abstract: The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit. Consequently, the output clock of the device has the same phase as that of the input clock IN and a constant duty ratio.

44 citations

Proceedings ArticleDOI
26 Mar 2007
TL;DR: An adaptive circuit technique is presented that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew, leading to much improved clock synchronization and design performance.
Abstract: On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance

44 citations

Patent
David L. Thompson1
09 Apr 1999
TL;DR: In this article, a data monitor is used to measure, sense or detect signals, inputs or outputs in a medical device before they are input to a principal or main digital signal processor, controller or microprocessor.
Abstract: Power consumption in medical and battery powered devices is reduced through the use and operation of a data monitor which measures, senses or detects signals, inputs or outputs in a medical device before they are input to a principal or main digital signal processor, controller or microprocessor. In response to detecting or measuring such a signal which meets certain amplitude, frequency and/or phase characteristics, the data monitor directs or controls clock or voltage supply circuits to increase or decrease clock frequency, or to increase or decrease the voltage provided to certain circuits within the medical device. The clock frequencies and/or voltages so employed are tailored to reduce the amount of power consumed by the medical device while preserving computational performance.

43 citations

Patent
Tyler J. Gomm1
11 Jun 2003
TL;DR: In this article, a clock signal generator providing an output clock signal synchronized with an input clock signal having a frequency dependent variable delay line to accommodate a wide range of operating frequencies is presented.
Abstract: A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate a wide range of operating frequencies. A clock signal synchronized with an input clock signal propagated through an input time delay and an output time delay is generated by delaying an input buffered clock signal by a first time delay based on the frequency of the input buffered clock signal, and further delaying the delayed input buffered clock signal by a second time delay to compensate for timing skew introduced by the input time delay, the output time delay and the process of delaying the input buffered clock signal.

43 citations

Patent
04 Sep 1998
TL;DR: In this article, the analog phase-locked loop is used for transmission and recovery of original digital data, which includes an encoder, a transmitter, a receiver, a decoder and an analog phase locked loop.
Abstract: A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1 % tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.

43 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202324
202231
202137
202050
201968
201884