Clock gating

About: Clock gating is a research topic. Over the lifetime, 7838 publications have been published within this topic receiving 107903 citations.

Self-checking digital fault detector for modular redundant real time clock

Abstract: A self-checking detector for detecting faults in a multiple redundant clock system includes a majority voter circuit for receiving the clock signals from the redundant clock circuits and for providing a voted output, a comparison circuit for comparing each of the clock signals with the voted output, and failure signal producing circuits responsive to the outputs from the comparison circuit for producing a first failure signal upon a clock failure being detected and for producing a second failure signal upon a failure of the majority voter being detected. The detector further includes power-up reset circuitry for inhibiting its operation during a power-up interval, and a reset circuit enabling either automatic or manual reset of the detector for verification of the detected fault.

Method and apparatus for establishing a system clock in response to the level of one of two clock signal sources

Abstract: A system clock is produced either from clock signals (t1) recovered in a clock regenerator, based on surface wave filtered technology and having level fluctuations, or from the digital clock signals (t2) internally generated in, for example, an access controller of a ring network, in response to the level of the regenerated clock signals (t1). The change in the source of the system clock is accomplished after an early detection of the level fluctuations, so that the clock signal (t1,t2) currently connected to the clock line are disconnected and, after a short delay time, the other clock signal (t1,t2) is sychronously switched to the clock line.

Globally asynchronous locally synchronous architecture for large high-performance ASICs

Abstract: Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%.

Clock controller for at-speed testing of scan circuits

Abstract: A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.

Clock generation and distribution in an emulation system

Abstract: A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.